Please enable JavaScript.
Coggle requires JavaScript to display documents.
Successive Approximation ADC - Coggle Diagram
Successive Approximation ADC
Circuit Components
SAR and Control Logic
Control logic sequences the tests
Successive approximation register stores trial bits
DAC and Comparator
DAC converts the trial code into a voltage
Comparator compares the voltage with the held input
Input Stability
Sample and Hold Circuit
Samples the input voltage
Hold it approximately constant during the conversion
Holding Reason
Every comparison needs to use the same input c
A changing input can invalidate the bit decisions
Performance
Hardware Efficiency
Avoids large comparator bank required by a high-res flash ADC
Uses a DAC, SAR, and comparator
Conversion Speed and Uses
Requires successive bit decisions
Suits high-res applications with moderate speed requirements
Conversion Steps
Initial Trial
DAC generates approx. half the full scale range
Set MSB to 1 and remaining bits to 0
Keep / Clear Each Bit
Keep the trial bit if input is at least the trial voltage.
Otherwise clear it; repeat for the next bit