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topic 1.1 systems architecture - Coggle Diagram
topic 1.1 systems architecture
von nueman
registors
MDR: hold the data or instruction tremporaly after it has been fetched
MAR: holds the memory adress of the intruction to be fetched
accumulator: hold the last instruction that has been done
holds the memory address of the next instruction
FDE cycle
instruction is fetched from main memory decoded in the control unit then instruction is then executed
Arithmetic logic unit
completes mathatical prosses
performs logic opirations and if statments
cache
stores frequently used instructions and is a tempory memory inbetween RAM and CPU
control unit
decodes instructions from the FDE cycle
1.1.2 CPU peformance
clock speed
how fast the CPU cand do the FDE cycle
number of cores
each core is a single prossesor