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Embedded System Hardware - Coggle Diagram

- - - - ARM THUMB (16-bit instruction mode) and MIPS16 achieve ~30% smaller code.
        
        RISC-V compressed extension reduces size by about 25%.
    - - Smaller memory requirement, lower power, and reduced bus traffic.
        
        Ideal for embedded devices like IoT sensors and smart controllers.
      - Applications
        
        Used in mobile devices, automotive controllers, and consumer electronics.
        
        Enables more features on low-cost microcontrollers.
  - - - Processors use shorter instruction encodings (e.g., 16-bit instead of 32-bit).
        
        Example: ARM THUMB or RISC-V C extensions use compact formats.
    - - Common instruction sequences are replaced by short codes that reference a dictionary.
        
        The dictionary is stored in memory and decompressed automatically during execution.
    - - Hardware decompressors expand code as it is fetched from memory.
        
        Allows execution of compressed code transparently without software delay.
    - - Remove redundant code, optimize loops, and improve instruction selection.
        
        The result is compact, energy-efficient, and faster executable code
    - - Combine features of RISC and CISC to achieve high performance with small code.
        
        Reduces instruction count without increasing decode complexity.
  - - - Processors use shorter instruction encodings (e.g., 16-bit instead of 32-bit).
        
        Example: ARM THUMB or RISC-V C extensions use compact formats.
    - - Common instruction sequences are replaced by short codes that reference a dictionary.
        
        The dictionary is stored in memory and decompressed automatically during execution.
    - - Hardware decompressors expand code as it is fetched from memory.
        
        Allows execution of compressed code transparently without software delay.
    - - Remove redundant code, optimize loops, and improve instruction selection.
        
        The result is compact, energy-efficient, and faster executable code
    - - Combine features of RISC and CISC to achieve high performance with small code.
        
        Reduces instruction count without increasing decode complexity.
  - - - It aims to make embedded software fit into small ROM or Flash memories.
        
        Smaller programs lower the system’s memory cost and power usage.
    - - Compact code improves system reliability and boot time.
        
        It also allows faster instruction fetching and better performance.
  - - - Frees up space for additional system functionality.
        
        Important for microcontrollers with limited Flash memory.
    - - Fewer instruction bytes fetched reduce memory energy and latency.
        
        Helps achieve faster response times in real-time systems.
    - - Compression should not disrupt branching or address calculations.
        
        Ensures smooth hardware and software integration.
    - - Hardware decompression must match instruction fetch speed.
        
        Ensures real-time execution without stalling.
    - - Compilers and debuggers must recognize compressed instructions.
        
        This helps maintain easy debugging and system maintenance.
  - - - Reducing code size minimizes the physical chip area required for storage.
        
        This directly decreases manufacturing cost and energy consumption.
    - - Smaller code reduces the number of memory fetch operations.
        
        Especially beneficial for systems using external Flash or EEPROM memory.
    - - Enables efficient use of SoC design space.
        
        Ideal for multi-function embedded applications.
- - - - Caused by transistor switching and charging/discharging internal capacitances.
        
        Depends on how often circuits switch, their load, and the supply voltage level.
    - - Caused by small leakage currents when transistors are off.
        
        Increases with higher temperature and smaller transistor sizes.
    - - Due to frequent data transfers and off-chip communication.
        
        Off-chip memory access consumes much more energy than on-chip operations.
  - - - Adjusts supply voltage and frequency to match workload demand.
        
        Reduces energy when full speed isn’t needed but slows execution slightly.
    - - Switches processor between run, idle, and sleep states.
        
        Used in processors like StrongARM to save significant energy.
    - - Turns off unused circuits or stops their clock signals.
        
        Helps minimize leakage and dynamic waste.
  - - - Lower power for longer times can still lead to high total energy.
        
        Designers focus on total energy per instruction or per task.
    - - Embedded processors aim for maximum operations per joule.
        
        Application-specific chips are the most efficient, followed by FPGAs and CPUs.
    - - Balancing energy and performance is key to embedded design.
        
        Trade-offs depend on workload and real-time deadlines.
  - - - The operating system adjusts processor activity based on workload.
        
        Tasks with lower urgency run at lower frequencies to save energy.
    - - Compilers rearrange code to reduce instruction count and memory accesses.
        
        Better instruction locality reduces memory and bus activity.
    - - Using multiple slow cores instead of one fast core can save energy.
        
        Lower speed reduces voltage needs and energy per operation.
  - - - Must balance energy saving and system response.
        
        Ideal settings depend on application timing constraints.
    - - ARM processors and Intel SpeedStep dynamically adjust power modes.
        
        Transmeta Crusoe used software-based power management effectively.
    - - Reduce off-chip memory accesses first, as they consume the most energy
        
        Use caching, compression, and efficient code to minimize fetch energy.