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Energy Efficiency - Coggle Diagram
Energy Efficiency
CMOS Circuits
Delay and power are interconnected
Gate capacitance affects switching energy
Low power logic design
Leakage power increases as nodes shrink
Parallel Execution
Energy per task drops when voltage is lowered
Enables task distribution
Multiple cores for faster processing
Must avoid overhead and idle cores
Dynamic Power Management (DPM)
Uses hardware and firmware policies
Monitors usage to save energy
Shuts down idle components
Trade-off between latency and power savings
Dynamic Voltage and Frequency Scaling (DVFS)
Requires voltage regulators and clock control
Balances performance vs energy
Saves power during low load
Adjusts CPU speed and voltage in real time
Power Consumption
Static Power
Grows with transistor count
Managed by power-gating and sleep modes
Caused by leakage current when idle
Major factor in deep-submicron CMOS
Dynamic Power
Formula: P = C × V² × f
Reduced by lowering voltage/frequency
Depends on voltage, frequency, and capacitance
Related to switching activity