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Components of a Computer - Coggle Diagram

- - - - alternating 1s + 0s million times a sec, synchronising CPU operations
        
        Clock switches from 0 to 1 = CPU operations start
  - - - Each core can process a different instruction
        
        Takes more power
        
        Software has to be able to take advantage
  - - - Fetched instruction copied into cache
        
        Quick access
        
        Unused data replaced by recent
  - - - Instruction pipeline
        
        Instruction is fetched, buffered and executed
      - Arithmetic pipline
        
        Parts of arithmetic operation that can be broken down and overlapped
- - - - PC
        
        Next instruction address
      - CIR
        
        Instruction being executed
      - MAR
        
        Holds address of instruction to be fetched/written to
      - MDR
        
        temporarily stores data read from/written to
    - - ALU output
  - - - Data Bus
        
        8/16/32/64 seperate lines, moves data + instructions bi-directionaly between componets
      - Address Bus
        
        Transmits memory addresses of words used as operands
        
        width determines the max capacity of the system
        
        Words
        
        fixed-size of bits processed as a single unit
      - Control Bus
        
        Bi-directional, transmits command/timing/status info between components
        
        Control Lines
        
        Bus Request
        
        device requests data bus
        
        Bus Grant
        
        grants access
        
        Memory Write
        
        data on data bus written to addressed location
        
        Memory Read
        
        data from addressed location put on data bus
        
        Interrupt Request
        
        shows a device requesting CPU access
        
        Clock
        
        Synchronises operations
  - - - Next instruction address taken from PC to MAR
        
        PC incremented
        
        Instruction at address written to MDR
        
        Instruction in MDR to CIR
        
        CIR instruction decoded
        
        Opcode
        
        Determines instruction type + hardware needed
        
        instruction/opcode executed on the operand
        
        1 more item...
        
        Operand
        
        Holds either
        
        3 more items...
- - - - Used with Digital Signal Processing (DSP)
      - instruction + data have separate memory and buses
      - memory can have different characteristics
      - instruction address bus may be wider than data bus
      - Faster than Von Neumann as less traffic
    - - 2 Processor Types
        
        RISC
        
        Simple
        
        1 instruction per clock cycle
        
        Disad: More work for compiler
        
        More RAM needed
        
        Adv: Pipelining possible
        
        CISC
        
        Complex
        
        Combines load/store instructions to 1
        
        MULT A, B == a = a*b
        
        Adv: Little work for compiler
        
        As code is short
        
        Little RAM to store instruction
        
        Disad: only 20% of instructions used
        
        Even tho loads built in hardware
      - Shared memory and bus used for both data + instructions
      - Program in main memory
        
        instructions fetched, decoded and executed 1 by 1
  - - - 1000s small cores handle tasks simultaneously
  - - - Limited range of functions
        
        floating point arithmetic
        
        Graphics processing
        
        Digital signal processing
        
        Unable to fetch own instructions
- - - - Highest £/GB
      - Very portable
      - Lower Capacity
      - Low Power
    - - Magnetic
        
        Tracks subdivided into sectors
        
        Drive Head moves across disk
      - Less portable
      - Largest Capacity