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Digital Design and Computer Architecture Chapter 1 From Zero to One -…
Digital Design and
Computer Architecture Chapter 1 From Zero to One
NUMBER SYSTEMS
1 . 4 .1 Decimal Numbers
1 . 4 . 2 Binary Numbers
1 . 4 . 3 Hexadecimal Numbers
1 . 4 . 4 Bytes, Nibbles, and All That Jazz
A group of eight bits is called a byte. It represents one of 28 256 possibilities. The size of objects stored in computer memories is customarily measured in bytes rather than bits.
1 . 4 . 5 Binary Addition
1 . 4 . 6 Signed Binary Numbers
1 . 5 LOGIC GATES
1 . 5 .1 NOT Gate
1 . 5 . 2 Buffer
It simply copies the input to the output.
-
From the logical point of view, a buffer is no different from a wire, so it might seem useless. However, from the analog point of view, the buffer might have desirable characteristics such as the ability to deliver large amounts of current to a motor or the ability to quickly send its output to many gates.
1 . 5 . 3 AND Gate
The Boolean equa-
tion for an AND gate can be written in several ways: Y=A•B, Y=AB, or Y A B. The symbol is pronounced “intersection” and is preferred by logicians
1 . 5 . 4 OR Gate
1 . 5 . 5 Other Two-Input Gates
1 . 5 . 6 Multiple-Input Gates
1 . 6 BENEATH THE DIGITAL ABSTRACTION
A digital system uses discrete-valued variables. However, the variables are represented by continuous physical quantities such as the voltage on a wire, the position of a gear, or the level of fluid in a cylinder. Hence, the designer must choose a way to relate the continuous value to the discrete value.
1 . 6 .1 Supply Voltage
Suppose the lowest voltage in the system is 0 V, also called ground or
GND
. The highest voltage in the system comes from the power supply and is usually called
VDD
.
-
In 1970’s and 1980’s technology,
VDD
was
generally 5 V. As chips have progressed to smaller transistors, VDD has dropped to 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, or even lower to save power and avoid overloading the transistors.
1 . 6 . 2 Logic Levels
The mapping of a continuous variable onto a discrete binary variable is done by defining logic levels, as shown in Figure 1.23. The first gate is called the
driver
and the second gate is called the
receiver
.
The driver produces voltages within certain ranges:
LOW (0): Voltage from 0V up to VOL
(the maximum voltage for logic 0).
HIGH (1): Voltage from VOH (the minimum voltage for logic 1) up to VDD
(the supply voltage, e.g., 5V).
The receiver interprets the signal using its thresholds:
If the voltage is between 0V and VIL, it is recognized as LOW (0).
If the voltage is between VIH and VDD, it is recognized as HIGH (1).
1 . 6 . 3 Noise Margins
Definition: Max noise tolerable on worst-case output before invalid input.
Requirement
:
VOL ≤ VIL & VOH ≥ VIH
(ensures clean handoff).
Formulas:
NML (Low Margin)
= VIL - VOL (tolerance for LOW signals).
-
NMH (High Margin)
= VOH - VIH (tolerance for HIGH signals).
Example 1.18 (Inverter Chain: I1 → I2, VDD=5V):
Specs: VIL=1.35V, VIH=3.15V, VOL=0.33V, VOH=3.84V.
Calc: NML=1.35-0.33=1.02V; NMH=3.84-3.15=0.69V.
Test 1V Noise:
LOW: Tolerates (0.33V +1V=1.33V <1.35V → still LOW).
HIGH: Fails (3.84V -1V=2.84V <3.15V → misread as LOW).
Insight: Asymmetric margins; design for balanced (e.g., via unity points).
Link: Maximized by Unity Gain Points in DC Transfer.
1 . 6 . 4 DC Transfer Characteristics
What It Is:
Output voltage (V(Y)) vs. Input voltage (V(A)) for slow-changing inputs (DC = steady-state).
Historical: From "direct current" (constant voltage).
Ideal Inverter:
Sharp transition at VDD/2 (e.g., <2.5V in → 5V out; >2.5V in → 0V out).
Perfect: VIH=VIL=VDD/2; VOH=VDD, VOL=0.
Real Inverter:
Smooth S-curve: Starts at V(Y)=VDD (V(A)=0), ends at V(Y)=0 (V(A)=VDD).
Not centered; gradual slope in middle.
Unity Gain Points: Where slope dV(Y)/dV(A) = -1 (small input change = equal output change).
Use: Defines optimal VIL/VIH (maximizes NML/NMH).
Benefit: If VIL too high → VOH drops sharply; too low → minimal gain.
Link: Basis for Static Discipline (ensures valid transfer).
1 . 6 . 4 DC Transfer Characteristics
What It Is: Output voltage (V(Y)) vs. Input voltage (V(A)) for slow-changing inputs (DC = steady-state).
Historical: From "direct current" (constant voltage).
Ideal Inverter:
Sharp transition at VDD/2 (e.g., <2.5V in → 5V out; >2.5V in → 0V out).
Perfect: VIH=VIL=VDD/2; VOH=VDD, VOL=0.
Real Inverter:
Smooth S-curve: Starts at V(Y)=VDD (V(A)=0), ends at V(Y)=0 (V(A)=VDD).
Not centered; gradual slope in middle.
Unity Gain Points: Where slope dV(Y)/dV(A) = -1 (small input change = equal output change).
Use: Defines optimal VIL/VIH (maximizes NML/NMH).
Benefit: If VIL too high → VOH drops sharply; too low → minimal gain.
Link: Basis for Static Discipline (ensures valid transfer).
