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ARM Architecture Fundamentals - Coggle Diagram
ARM Architecture Fundamentals
Applications processor roadmap
Classic ARM Processors
ARM7EJ-S
ARM926EJ-S
ARM1136J(F)-S
ARM1176JZ(F)-S
ARM11MP
Application Cortex Processors
Cortex-A5
Cortex-A7
Cortex-A8
Cortex-A15
Inside an ARM based system
ARM Processor Core:
The central component, marked in blue,
which handles the main processing tasks.
-
Connects to other components via the AXI (Advanced eXtensible Interface) protocol, an efficient communication standard developed by ARM.
Clocks and Reset Controller:
Marked in pink, this component provides clock signals and manages system resets to ensure synchronized and stable operation.
CoreLink Interrupt Controller:
Marked in orange, it manages interrupt signals from peripherals and sends them to the ARM core for handling unexpected or prioritized events.
Other CoreLink Peripherals:
Also in orange, these are integrated peripherals (e.g., timers, counters) that support additional functionalities.
Custom Peripherals:
Marked in pink, these are application-specific components designed based on the SoC manufacturer's needs
MBA (Advanced Microcontroller Bus Architecture):
The primary communication protocol, including:
AXI
: Connects the ARM core to components like memory and the DMA interface.
-
APB
(Advanced Peripheral Bus): Connects peripherals to the bridge for low-speed, energy-efficient data transfer.
-
Bridge
: Links different protocols (e.g., AXI and APB) for compatibility.
DMA Port:
Marked in orange, it enables direct data transfer between memory and peripherals without involving the core, improving efficiency.*
External Memory Interface:
Connects to external memory such as FLASH and SDRAM.
FLASH and SDRAM:
Marked in pink:
FLASH
: Stores programs and non-volatile data.
-
SDRAM
: Provides volatile memory for temporary data during operation.
On-chip memory:
Integrated on the SoC, offering fast memory for immediate tasks.
JTAG/SWD (Debugging Protocol):
Used for debugging and programming the hardware.
nIRQ (Non-Maskable Interrupt):
Sends critical interrupt signals from the interrupt controller to the ARM core.
Development of the ARM architecture
Version v4T:
Features
: Support for halfword and signed halfword/byte, system mode, Thumb instruction set.
-
Processor
: ARM7TDMI-S, commonly used in basic embedded devices.
Version v5TE:
Features
: Improved ARM/Thumb interworking, CLZ (Count Leading Zeros), saturated arithmetic, and DSP (digital signal processing) instructions.
-
Processor
: ARM926EJ-S, suitable for more complex embedded applications.
Version v6:
Features
: SIMD (Single Instruction, Multiple Data) support, multiprocessing, v6 memory architecture, unaligned data support, and extensions like Thumb-2 (v6T2), TrustZone (v6Z), multicore (v6K), and Thumb-only (v6-M).
-
Processor
: ARM1136J(F)-S, targeted at mobile and multimedia devices.
Version v7:
Features
: Support for Thumb-2, NEON (multimedia acceleration unit), TrustZone (security), and virtualization.
Architecture Profiles:
-
v7-A (Applications)
: For high-performance applications, integrated with NEON.
-
v7-R (Real-time):
For real-time applications, with hardware divide support.
-
v7-M (Microcontroller)
: For microcontrollers, with Thumb-2 and hardware divide support.
Cortex Line
: Introduced as a low-power leadership, including cores like Cortex-A8 and Cortex-A9 with 13-stage or 8-stage pipelines.
Architecture profiles of the ARM Architecture v7
ARMv7-A
(Application),
ARMv7-R
(Real-time), and
ARMv7-M/ARMv6-M
(Microcontroller)
Application profile (ARMv7-A):
Features:
Memory management support (MMU - Memory Management Unit).
-
Highest performance at low power.
-
Influenced by multi-tasking OS system requirements.
-
TrustZone for a safe, extensible system.
-
Optional Large Physical Address and Virtualization extensions.
Cortex Cores
:
Cortex-A15:
Supports NEON, multi-core (1-4 cores), L2 Cache, and AXI protocol.
-
Cortex-A9:
Supports NEON, multi-core (1-4 cores), cache, and AXI protocol.
Real-time profile (ARMv7-R):
Features
:
Protected memory (MPU - Memory Protection Unit).
-
Low latency and predictability for 'real-time' needs.
-
Tightly Coupled Memories for fast, deterministic access.
Cortex Cores:
Cortex-R4:
Single-core support, cache, and AXI protocol.
-
Cortex-R5MP:
Multi-core support, cache, and AXI protocol.
Microcontroller profile (ARMv7-M, ARMv6-M):
Features:
Lowest gate count entry point.
Deterministic and predictable behavior a key priority.
Deeply embedded use.
Cortex Cores:
Cortex-M3: Single-core, Flash memory, and AHB-Lite protocol.
Cortex-M0: Single-core, Flash memory, and AHB-Lite protocol.
Cortex-M0+: Optimized with AHB-Lite protocol and low-latency buffer.
Data sizes (Data Sizes) and instruction sets (Instruction Sets)
Fundamental Characteristics of ARM Architecture:
ARM is a RISC architecture
: Most instructions execute in a single cycle, with an orthogonal register set and a load-store architecture (memory access is limited to load and store operations).
-
ARM is a
32-bit load-store architecture
:
The only memory accesses allowed are loads and stores.
Most internal registers are 32 bits wide.
Data Sizes:
When used in relation to ARM:
Word
: 32 bits (four bytes).
-
Halfword
: 16 bits (two bytes).
-
Doubleword
: 64 bits (eight bytes).
Instruction Sets:
Most ARM cores implement two instruction sets:
32-bit ARM Instruction Set:
The primary set, optimized for high performance.
-
16/32-bit Thumb Instruction Set:
A compressed set to reduce code size, suitable for embedded devices.
-
Older cores:
Support only 16-bit Thumb instructions.
Thumb-2 technology: In current cores, adds 32-bit instructions to Thumb, maintaining code density while increasing flexibility.
Processor Modes of ARM cores Cortex-M
General Characteristics:
Most ARM cores have seven basic operating modes.
-
Each mode has access to its own stack space and a different subset of registers.
-
Some operations can only be carried out in a privileged mode.
Supervisor (SVC):
Entered on reset and when a Supervisor Call Instruction (SVC) is executed.
Privileged mode.
FIQ (Fast Interrupt Request):
Entered when a high priority (fast) interrupt is raised.
Privileged mode.
IRQ (Interrupt Request):
Entered when a normal priority interrupt is raised.
Privileged mode.
Abort:
Used to handle memory access violations.
Privileged mode.
Undef (Undefined):
Used to handle undefined instructions.
Privileged mode.
System:
Privileged mode using the same registers as User mode.
User:
Unprivileged mode under which most Applications / OS tasks run.
Classification:
Exception modes:
Includes Supervisor, FIQ, IRQ, Abort, and Undef, which are privileged modes for handling exceptions.
-
Unprivileged mode:
Includes User, this mode restricts access to ensure system safety.
Thread Mode:
Description
: This mode runs application code (Application Code).
-
Transition
: Switches to Handler Mode when an exception occurs.
-
Purpose
: Used to execute normal application tasks.
Handler Mode:
Description
: This mode runs exception handlers (Exception Handlers).
-
Transition
: Activated on exception entry (Exception Entry) and returns to Thread Mode after processing (Exception Return).
-
Purpose
: Handles exceptional events such as interrupts or errors.
-
Register Structure:
Common registers (r0-r7):
These registers are shared across all modes, known as "Thumb state low registers".
-
Additional registers (r8-r12):
In FIQ mode, r8-r12 are private, while other modes share them with User mode.
-
Banked registers (r13, r14):
r13 is typically used as the stack pointer (sp).
-
r14 is usually the link register (lr), storing the return address.
Each mode except User/System has its own r13 and r14 to preserve context during mode switches.
r15 (pc):
The program counter register, shared across all modes.
-
cpsr (Current Program Status Register):
The current status register, shared across all modes, containing condition flags and mode status.
-
spsr (Saved Program Status Register):
The saved status register, available only in exception modes (FIQ, IRQ, SVC, Undef, Abort) to store the cpsr state before mode switching.`
