Please enable JavaScript.
Coggle requires JavaScript to display documents.
Modern Computer Architecture - Coggle Diagram
Modern Computer Architecture
Five Classical Components:
Input
Output
Memory
Datapath ↔ Control Unit (Connected visually as part of the CPU)
Instruction Set Architecture:
Categories of Instructions
Types of Operations (Arithmetic, Logical, Control)
Operand Types
Number Representations (e.g.,
Two's Complement, Floating Point
)
Instruction Execution:
Instruction Cycle
Datapath & Control Flow
Pipelining
Hazards: Data, Control, Structural
Memory Hierarchy:
Registers
L1, L2, L3 Cache
Main Memory (DRAM)
Secondary Storage (SSD/HDD)
Archival Storage (Tape/Cloud)
Memory Locality (Temporal & Spatial)
Optimization Techniques (Caching, Prefetching)
Parallelism in Architecture:
SISD
(example: Basic embedded CPU)
SIMD
(example: GPU)
MIMD
(example: Multi-core server)
SPMD
(example: Supercomputer)
Five Classical Components:
Input:
Definition: Sends data and commands into the system.
Examples: Keyboard, Mouse, Scanner
Output
Definition: Sends processed results to the user.
Examples: Monitor, Printer, Speaker
Memory
Definition: Stores data and instructions temporarily or permanently.
Examples: RAM, Cache, Hard Disk Drive (HDD)
CPU (Group Node: Datapath + Control Unit)
Datapath
Contains: ALU (Arithmetic Logic Unit)
Function: Performs computations and data transfers.
Control Unit
Function: Interprets instructions from memory and coordinates operations of datapath, memory, and I/O.
Instruction Set Architecture
Instruction Categories
Data Transfer (e.g., load, store)
Arithmetic/Logical (e.g., add, sub, and, or)
Control Flow (e.g., branch, jump, call)
Memory Access (e.g., lw, sw in MIPS)
Operation Types
Arithmetic (Addition, Subtraction, Multiplication, Division)
Logical (AND, OR, XOR, NOT)
Control (Branches, Loops, Function Calls)
Shift/Rotate (e.g., shift left, shift right)
Operand Types
Immediate (constant value embedded in instruction)
Register (value stored in CPU register)
Memory (value accessed from memory address)
Number Representations
Unsigned Binary
Two’s Complement (for signed integers)
Fixed Point (used in some embedded systems)
Floating Point (IEEE 754)
Instruction Execution
Instruction Cycle (Basic Stages)
Fetch (Instruction fetched from memory)
Decode (Instruction type identified; operands located)
Execute (ALU processes operation)
Memory Access (if needed for load/store)
Writeback (result saved to register or memory)
Datapath & Control Flow
Datapath: Includes ALU, Registers, Buses
Control Unit: Coordinates the timing and flow of data
Interconnection: Managed via control signals
Performance Techniques
Pipelining: Overlapping stages to increase throughput
Instruction 1 in Execute, Instruction 2 in Decode, etc.
Hazard Handling:
Data Hazard: One instruction depends on result of another
Control Hazard: Branching affects what should be fetched next
Structural Hazard: Two instructions need same hardware at once
Clocking
Synchronous Execution: Timed to clock cycles
Cycle Time Optimization: Aim to minimize delay per stage
Memory Hierarchy
Levels of Hierarchy (Top-down structure)
Expanded view of memory system
Registers
Inside CPU
Fastest, smallest (1 CPU cycle)
L1 Cache
Closest to CPU core
32–128KB, SRAM, ~1–5 cycles
L2 Cache
On-chip or near-chip
~256KB–1MB, ~5–20 cycles
L3 Cache
Shared among cores
Larger (~2MB–50MB), ~20–50 cycles
Main Memory (DRAM)
GBs in size
~100+ CPU cycles
Secondary Storage
SSDs, HDDs
Slower, used for long-term storage
Archival Storage
Magnetic tape, cloud backup
Used for archiving — large, cheap, slow
Overview
Purpose: Balance speed and cost by organizing memory into levels.
Key Concepts
Speed vs. Size vs. Cost per Bit
Temporal & Spatial Locality
CPU must stay busy — reduce access delays
Optimization Techniques
Caching
Prefetching
Compiler & Hardware Support
Memory Locality
Temporal: recently used data is likely to be reused
Spatial: nearby data is likely to be accessed soon
Parallelism in Architecture
Why Parallelism?
Goal: Increase performance by executing multiple operations simultaneously
Helps with:
High throughput
Efficiency
Scalability (e.g., in multicore systems)
Key Concepts:
Instruction-Level Parallelism (ILP)
Data-Level Parallelism (DLP)
Thread-Level Parallelism (TLP)
Amdahl’s Law — limits to speedup due to serial code portions
Parallel Architecture Types
SISD
– Single Instruction, Single Data
Sequential execution
Example: Basic embedded system or old CPU
SIMD
– Single Instruction, Multiple Data
Same instruction applied across multiple data elements
Example: GPU processing multiple pixels
MIMD
– Multiple Instruction, Multiple Data
Independent cores executing different instructions on different data
Example: Server with multiple CPUs
SPMD
– Single Program, Multiple Data
Same program, different data sets across processors
Example: Supercomputer running distributed simulations
MISD
Not commonly used — inefficiencies from running multiple instructions on same data stream
Used for: Fault tolerance, rarely in general computing