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TDT01 - Coggle Diagram
TDT01
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R-HLS
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HLS need to identify all depentencies hence beneficial with IR, RVSDG is an alternative
R-HLS is an RVSDG dialect for dynamic HLS. RVSDG is a general IR and don't have too much to do with HLS
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Replaces given structures with own. Example introduces HLS-LOOP which replaces theta node and exposes the required routing and control logic for generating hardware
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FIRRTL
In general, there is a lack of hardware libs and hardware is therefore rarely reused
Reasons might be the lack of expressivity as the HDL haven't developed fast especially compared to software languages
They made Verilog in 2k2 seems dogshit as it makes program unnecessary complicated and there is no compiler implementing the whole spec
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Evaluation
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So much of the point here really is the fact that FIRRTLE thanks to its rich IR should be able to enable consise expressions with less lines of code?
One great point is the fact that synthesizing for the SRAM takes much shorter time then with registers
Memory replacement transfort replaces a generic FIRRTL memory with a custom black box that matches the ports of the vendor provided SRAM