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Innovus Basic Flow - Coggle Diagram
Innovus Basic Flow
Placemnet
Legalization
Detail Placement
Global Placement
Placement bounds
initial
output
Technology File (.tf)
RC Module Files (TLU+)
Physical Library File (.lef/mw/OA)
Input
Constrants Files (.sdc) (DATA_IN)
Gate_level Netlist (.v)
Logic/timing Library Files (.db/.lib) (setup.tcl)
Tech file (setup.tcl)
Physical Library Files (.lef) (setup.tcl)
TLU+ (setup.tcl)
mmmc file
upf (DATA_IN)
Flow
Kiểm tra source file var.tcl
var.tcl: chứa tất cả các biến cần sử dụng cho quá trình PnR
Kiểm và source config_files
setup.tcl
design_name, top_layout, netlisst, ...
innovus_config.tcl
difine: dont_use_list, tie_cells, filler_cells, ..
lp_config.tcl
source proc.tcl
proc.tcl: chứa các hàm tái sử dụng
source innit
set file netlist
set mmmc_file
set top_cell
set gnd_net
set power_net
read_power_intent
include information power connection (create_supply_port,net, connect) in DATAin File
source sdc
sdc from synthesis
set_clock_uncertainty
set_in/output_delay
create_clock
case_analysis
false_path
multi_cyclepath
Floorplan
Goals of Floorplan
Routale
Good for timing optimization
Miniminal chip size
Strong (enough) Power and Ground
What will we do?
Routing
CTS
Chip Finish