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1.1.1 Mindmap - Coggle Diagram

- - - - Future requests for that data can be fulfilled faster
  - - - Up to three instructions, fetched, decoded and executed simultaneously - different stage of the cycle
  - - - Can be increased through overclocking
- - - - Holds the address of the next instruction to be executed
    - - Holds the address of the memory location from which data/an instruction is to be fetched/data is to be written to
      - Sends these address' to memory down the address bus
    - - Used to temporarily store data written from/written to memory
      - All data to/from memory must travel down data bus + pass through MDR
    - - Holds the current instruction being executed
      - Contents of MDR copied to CIR if it is an instruction
      - Contains opcode + operand(s) of current instruction
        
        Instruction = opcode + operand(s)
        
        Opcode is WHAT is to be
        
        Operand is WHERE to find/store data/instructions
    - - Temporarily stores the results of the ALU
  - - - Carries command and control signals to/from other components of CPU/computer
        
        Bidirectional
    - - Carries memory addresses identifying where data is being read from/written to
        
        Unidirectional
    - - Carries binary values making up the instruction/data
        
        BIdirectional