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TSMC images - Coggle Diagram

- - - - Design and Technology Platform
      - IT, Material Mgt. & Risk Mgt.
      - Research & Development
      - Human Resource
      - Corp. Development
      - World Wide Sales & Services
      - Quality & Reliabilty
      - Corp. Planning
      - Operation II
      - Legal
      - Operations I
      - Finance
      - TSMC Shanghai
      - Wafer Tech
- - - - Premium Mobile, Data Center, Server,
        AI Accelerator, Game, ADAS
        
        2021: N5P, N7A
        
        2020: N5
        
        2019: N7+
        
        2022: N4
        
        2018: N7
        
        2023: N3, N4P, N4X
        
        2024: N3E, N5A
        
        2025: N2, N3P, N3X
        
        2026: N2P, N2X, N3A
    - - Mid-to-low-end Mobile, Consumer,
        Base Station, Networking
        
        2021: N6
        
        2024: N4P
        
        2020: 12FFC+, 16FFC+
        
        2026: N3P
        
        2018: 12FFC
  - - - RF (Radio Frequency)
      - High-voltage
      - Low-power
      - Mixed-signal
      - Embedded non-volatile memory (NVM)
      - Bipolar-CMOS-DMOS (BCD)
      - High-performance analog
    - - Advanced packaging technologies
        
        CoWoS (Chip on Wafer on Substrate)
        
        InFO (Integrated Fan-Out)
        
        2.5D and 3D packaging solutions
        
        Chiplet integration technologies
      - System-level packaging
        
        Multi-chip modules (MCMs)
        
        Heterogeneous integration solutions
        
        System-in-Package (SiP) solutions
      - Design services
        
        Design ecosystem partnerships
        
        Design enablement services
        
        IP (Intellectual Property) integration support
      - Testing and validation
        
        Advanced testing methodologies
        
        Reliability testing services
        
        Yield optimization solutions
      - System integration support
        
        System integration consulting
        
        System-level design verification
        
        Performance optimization services
    - - CoWoS (Chip on Wafer on Substrate)
        
        Advanced packaging technology enabling integration of multiple chips on a single substrate
        
        Enables higher bandwidth and performance for complex semiconductor designs
      - InFO (Integrated Fan-Out)
        
        Advanced packaging technology allowing for compact and high-performance chip integration
        
        Provides improved thermal performance and power efficiency compared to traditional packaging methods
      - 2.5D and 3D packaging solutions
        
        Integration of multiple chips using advanced stacking and interconnection techniques
        
        Enables higher levels of performance and functionality in compact form factors
      - Chiplet integration technologies
        
        Facilitates the integration of semiconductor "chiplets" from different manufacturers into a single package
        
        Allows for modular design and reusability of chip components, enhancing flexibility and scalability
      - System-in-Package (SiP) solutions
        
        Integration of multiple semiconductor components, including chips, passive components, and subsystems, into a single package
        
        Enables miniaturization and performance optimization for complex systems
      - Multi-chip modules (MCMs)
        
        Packaging solutions that integrate multiple chips onto a single module, typically for high-performance computing applications
        
        Offers enhanced performance, bandwidth, and scalability compared to single-chip solutions
      - Heterogeneous integration solutions
        
        Integration of chips with different technologies (e.g., logic, memory, sensors) into a single package.
        
        Enables the development of highly integrated and specialized systems for specific applications
    - - 7nm
      - 16nm
      - 28nm
      - 40nm
      - 20nm
      - 5nm