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computer design - Coggle Diagram

- - - - hold key local variables and intermediate results of calculations
    - - includes things
        like the program counter and stack pointer
  - - - read after write (RAW)
      - write after read (WAR)
      - write after write (WAW)
      - = when instructions write and/or read same register/mem in different stages of a pipeline
    - - = when instructions that are already in pipeline need the same resource, e.g. single ALU or single LOAD port on main memory
    - - = makes wrong decisions on branch prediction -> instructions must be discarded
  - - - set-associative
        
        definition
        
        assign -> any matching set ID, empty cache line with tag = block ID and all columns = block values
        
        search -> all matching set ID cache line for tag == block ID, if so get value in column = word ID
        
        analogy
        
        assign -> item to numbered room
        
        check -> whole numbered room
        
        address = block ID + set ID + word ID
      - fully associative
        
        analogy
        
        check -> whole room
        
        assign -> item anywhere in a room
        
        operation
        
        assign -> any empty cache line, if so set tag = block ID and all columns = block values
        
        check -> all cache lines for tag == block ID, if so get value in column = word ID
        
        address = block ID + word ID
      - direct-mapped
        
        analogy
        
        check -> numbered locker
        
        assign -> item to numbered locker
        
        definition
        
        assign -> matching line ID cache line with tag = block ID and all columns = block values
        
        check ->matching line ID cache line for tag == block ID, if so get value in column = word ID
        
        address = block ID + line ID + word ID
    - - write through
        
        every write to cache is also a write to main memory
      - write back
        
        update main memory only when dirty line is replaced
    - - Type (T): is it data or instruction?
      - Valid (V): does it contains actual (valid) elements?
      - Lock (L): Is it locked to prevent replacement (e.g. operation system)?
      - Dirty (D): is it written to but not updated in main memory?
  - - - memory location used -> same location will likely be used again
    - - memory location used -> nearby locations will likely be used
  - - - flush
        
        = convert invalid instructions (e.g. wrong branch prediction, after jump that hasn't triggered) in pipeline stages to bubles
      - bubble, stall, break
        
        = delay execution of an instruction
    - - operand forwarding
        
        = copy data from later stages' result instead of accessing memory
      - out-of-order execution
        
        = execute instructions out of order
    - - branch prediction
        
        = guess which instructions to insert -> pipeline bubble only needed if incorrect
  - - - Does not have a master clock. Bus cycles can
        be any length and not equal
      - handshake
        
        master sends a ready/sync signal after memory address has been sent and when it have received the data it stops the signal before the address signal stops after
        
        slave receives that and responds with its ready signal and works until it is done and have send the data and turns off the signal
    - - Driven by a master clock. Bus activities take an number of cyles of the clock.
    - - when you have multiple masters, the aribtre chooses how to allocate the bus
      - centralized
        
        daisy chain arbitration
        
        the grant line is going through every device, and the request line is shared so if multiple is requesting, the requesting device closest to the arbitrer is granted
        
        single arbiter controls bus
      - decentralized
        
        distributed arbitration by self-control
        
        there is a busy line aswell, so every device can check the busy line and if it is not busy, you can make it busy and become the master and send requests via the request line
        
        the devices control the bus themselves
    - - master can request from and send data to others
      - slave can only listen to master orders and execute it