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FOSS PDK EDA/CAD - Coggle Diagram

- - - - Passive
        
        S-Par
      - Active
        
        MOSFET
        
        BJT
  - - - PyCell API
- - - - Open Road
      - Yosys + ABC
      - OpenSTA
  - - - Magic
      - kLayout
        
        GDSII
        
        DRC
        
        LVS
        
        Parasitic Extraction
        
        Parameterizable cells
        
        Physical Verification
    - - Qucs
      - revEDA
      - xSchem
    - - ngspice
        
        Native C-code Models
        
        OpenVAF
        
        Verilog-A Models
      - Qucs
      - Xyce
  - - - Python scripting
        or Octave
      - mesh (CSXCAD
      - S-Par

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FOSS
PDK EDA/CAD

Matching

OpenPDK

EDA/CAD

Digital

Analog/RF

Layout Editors

Schematic Entry

Qucs

revEDA

Magic

kLayout

Simulators

ngspice

Qucs

Xyce

EM Simulators

OpemEMS

SPICE Lib

pCells

Device Models

Corners

Matching

Devices

Digital Blocks

Open Line

Analog/RF Blocks

Passive

Active

MOSFET

BJT

GDSII

DRC

LVS

Parasitic Extraction

Native C-code Models

OpenVAF

Temperature

Digital

Liberty Timing File (LIB)

S-Par

Library Exchange Format (LEF)

Design Exchange Format (DEF)

PyCell API

IO Cells

Open Road

Yosys + ABC

OpenSTA

Parameterizable cells

Physical Verification

Python scripting
or Octave

mesh (CSXCAD

S-Par

Verilog-A Models

xSchem

IP

Analog

Digital