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FOSS PDK EDA/CAD - Coggle Diagram
FOSS
PDK EDA/CAD
OpenPDK
SPICE Lib
Device Models
Passive
S-Par
Active
MOSFET
BJT
Corners
Matching
Temperature
pCells
Devices
PyCell API
Digital Blocks
Analog/RF Blocks
IO Cells
Digital
Liberty Timing File (LIB)
Library Exchange Format (LEF)
Design Exchange Format (DEF)
IP
Analog
Digital
EDA/CAD
Digital
Open Line
Open Road
Yosys + ABC
OpenSTA
Analog/RF
Layout Editors
Magic
kLayout
GDSII
DRC
LVS
Parasitic Extraction
Parameterizable cells
Physical Verification
Schematic Entry
Qucs
revEDA
xSchem
Simulators
ngspice
Native C-code Models
OpenVAF
Verilog-A Models
Qucs
Xyce
EM Simulators
OpemEMS
Python scripting
or Octave
mesh (CSXCAD
S-Par