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Building Timing Predictable Embedded Systems, Aluno: Alexandre Nadolni…
Building Timing Predictable Embedded Systems
Fundamental Predictability Concepts
Key Aspects
sources of uncertainty: input, hardware state
quality measure
inherent to system
Template
BCET: Best-Case Execution Time
WCET: Worst-Case Execution Time
Timing Predictability
State-Induced Timing Predictability
Input-Induced Timing Predictability
Tp(q,i): execution time of program p starting in state q with input i
Microarchitecture
Classification
Fully timing compositional architectures
no timing or domino
Compositional architectures with constant-bounded effects
timing but no domino
Noncompositional architectures
timing and domino
Timing Anomalies
local WC doesn't affect global WC
cache miss and branch prediction
schedule
cache
Domino Effects
difference in execution time between states proportional to path's length
Pipelines
Contributions to Complexity
super-scalar, out-of-order, buffer size, dynamic branch prediction, cache-like structures, branch history tables
instructions need to be considered collectively
exclude as many timing accidents as possible
Multithreading
Real-time thread with priority
Virtual multiprocessor: static scheduling
PTARM: four hardware threads interleaved
Caches and Scratchpad Memories
Influence of Cache Replacement Policy
State-Induced Cache Predictability
FIFO and PLRU affected by states. LRU robust
Interference on Shared Caches
Depends on memory access of other applications
Scratchpad Memories (SPM)
Static Random Access Memory (SRAM)
software controlled
Dynamic Random Access Memory (DRAM)
need to be refreshed
Synchronous Programming Languages for Predictable Systems
Approach to Predictability
Logical ticks
Interleaving
Need to be faster than environment
Worst-Case Response Time (WCRT)
No pointers, recursive data structures, dynamic memory allocation, assignments with side effects, recursive functions and variable length loop
Language Constructs to Express Synchrony and Timing
Berkeley-Columbia PRET Language
Dead(t): wait t cycles since last Dead
Synchronous C and PRET-C
ISA for Synchronous Programming
Reactive processors
WCRT for Synchronous Programs
Includes preemption and concurrency
Compilation for Timing Predictable Systems
Fundamentals of WCET-aware Compílation
Integration of Static WCET Analysis into the Compíler
Specification of Memory Hierarchies
Usually delegated to linker
Flow Fact Specification and Trasnformation
User annotations
Affected by optimizations
Examples of WCET-aware Optimizations
Scratchpad Memory Allocation and Cache Locking
Code Positioning
reduce I-cache misses
Cache Partitioning for Multitask Systems
Building Real-Time Applications on Multicores
Timing Interferences and Isolation
Joint Analysis
all tasks together
Spatial and Temporal Isolation
Singe core analysis if tasks are isolated
System-Level Scheduling and Analysis
Global Scheduling
critical instant
Partitioned Scheduling
Reliability Issues in Predictable Systems
probabilistic threshold
Controller Area Network (CAN)
Cyclic Redundancy Checks (CRC)
Retransmission
Predictability for Fault-Tolerant Architectures
hardware redundancy
Forward Error Correction (FEC)
Error Correcting Codes (ECC)
Aluno: Alexandre Nadolni Bonacim
