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REDUCED INSTRUCTION SET COMPUTERS - Coggle Diagram
REDUCED INSTRUCTION
SET COMPUTERS
MIPS R4000
Instruction Set
Instruction Pipeline
Eight pipeline stages of R4000
Five pipeline stages of R3000
Reduced Instruction Set Architecture
Characteristics of Reduced Instruction Set Architectures
CISC versus RISC Characteristics
Not clear cut
Many designs borrow from both philosophies
Why CISC
Faster programs
CISC will yield smaller programs
Compiler Simplification
The Use of a Large Register File
Global Variables
Allocated by the compiler to memory
Have a set of registers for global variables
Large Register File Versus Cache
Large Regiter File
Cache
Register Windows
Three areas within a register set
Multiple small sets of registers
Limited range of depth of call
Temporary registers from one set overlap
parameter registers from the next
Function calls only uses few parameters
Handles n-depth procedure calls
Compiler -Based Register Optimization
For each program, list possible variable candidates which can be register
Map (unlimited) symbolic registers to real registers
HLL programs have no explicit references to registers
Symbolic registers that do not overlap can share real registers
Optimizing use is up to compiler
Optimization task -> determine which variable can be assigned to real register
SPARC
Instruction Set
Instruction Format
SPARC Register Set
RISC versus CISC Controversy
Qualitative
Several problems
Quantitative
Instruction Execution Characteristics
Operations
Operands
Execution Characteristics
Procedure Calls
Intention of CISC
Implications
Risc Pipelining
Pipelining with regular instructions
Two phases of execution
Most instructions are register to register
For load and store
Effects of pipelining
Optimization of pipelining
Delayed load
Loop unrolling
Delayed branch