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PROCESSOR STRUCTURE AND FUNCTION - Coggle Diagram
PROCESSOR STRUCTURE
AND FUNCTION
Instruction Cycle
The Indirect Cycle
Data Flow
Processor Organization
Process data
Fetch data
Interpret instruction
Write data
Fetch instruction
Instruction Pipelining
Pipeline Hazards
DATA HAZARDS
CONTROL HAZARDS
RESOURCE HAZARDS
Dealing with Branches
Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch
Pipeline Performance
Intel 80486 Pipelining
Decode stage 2
Execute
Decode stage 1
Write back
Fetch
Pipelining Strategy
Calculate operands (CO)
Fetch operands (FO)
Decode instruction (DI):
Execute instruction (EI)
Fetch instruction (FI)
Write operand (WO)
The ARM Processor
Processor Modes
Undefined mode
Fast interrupt mode
Abort mode
Interrupt mode
Supervisor mode
Register Organization
GENERAL-PURPOSE REGISTERS
PROGRAM STATUS REGISTERS
Processor Organization
Interrupt Processing
FIQ (fast interrupt)
IRQ (interrupt)
Data abort
Prefetch abort
Reset
Undefined instructions
Software interrupt
Register Organization
Control and Status Registers
Memory address register (MAR)
Instruction register (IR)
Memory buffer register (MBR)
Program counter (PC)
Example Microprocessor Register Organizations
User-Visible Registers
Address
Data
General Purpose
Condition Codes
The x86 Processor Family
Register Organization
Segment
General
Interrupt Processing
INTERRUPT VECTOR TABLE
INTERRUPT HANDLING
INTERRUPTS AND EXCEPTIONS