PROCESSOR STRUCTURE
AND FUNCTION
Instruction Cycle
Processor Organization
Instruction Pipelining
The ARM Processor
Register Organization
The x86 Processor Family
Control and Status Registers
Example Microprocessor Register Organizations
User-Visible Registers
The Indirect Cycle
Data Flow
Pipeline Hazards
Dealing with Branches
Pipeline Performance
Intel 80486 Pipelining
Pipelining Strategy
Register Organization
Interrupt Processing
Processor Modes
Register Organization
Processor Organization
Interrupt Processing
Process data
Fetch data
Interpret instruction
Write data
Fetch instruction
Address
Data
General Purpose
Condition Codes
Memory address register (MAR)
Instruction register (IR)
Memory buffer register (MBR)
Program counter (PC)
Calculate operands (CO)
Fetch operands (FO)
Decode instruction (DI):
Execute instruction (EI)
Fetch instruction (FI)
Write operand (WO)
DATA HAZARDS
CONTROL HAZARDS
RESOURCE HAZARDS
Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch
Decode stage 2
Execute
Decode stage 1
Write back
Fetch
Segment
General
INTERRUPT VECTOR TABLE
INTERRUPT HANDLING
INTERRUPTS AND EXCEPTIONS
Undefined mode
Fast interrupt mode
Abort mode
Interrupt mode
Supervisor mode
GENERAL-PURPOSE REGISTERS
PROGRAM STATUS REGISTERS
FIQ (fast interrupt)
IRQ (interrupt)
Data abort
Prefetch abort
Reset
Undefined instructions
Software interrupt