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Control Unit Operation, - Coggle Diagram
Control Unit Operation
Hardwired Implementation
Control Unit Inputs
Flags and control bus
Clock
Instruction register
Control Unit Logic
Micro-Operations
The Interrupt Cycle
The Execute Cycle
ADD
ISZ
BSA
The Instruction Cycle
Instruction cycle code (ICC)
01: Indirect
10: Execute
00: Fetch
11: Interrupt
The Fetch Cycle
Fetch Sequence (symbolic)
Clock Cycle Grouping
4 registers
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Control of the Processor
Internal Processor Organization
Control signals
Gates
Temporary registers
Control Signals
Output
Within CPU
Via control bus
To memory
To I/O modules
Inputs
Flags
Results of previous operations
State of CPU
Op-code for current instruction
From control bus
Interrupts
Acknowledgements
Clock
Functional Requirements
Describe micro-operations processor performs
Transfer data from register to external
Transfer data from external to register
Transfer data between registers
Perform arithmetic or logical ops
Define basic elements of processor
Registers
ALU
Internal data paths
External data paths
Control Unit
Determine functions control unit must perform
Execution
Sequencing (flow control)
The Intel 8085
Incrementer/decrementer address latch
Interrupt control
Serial I/O control
A Control Signals Example
Fetch
Indirect
Interrupt