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Parallel Processing Architectures - Coggle Diagram
Parallel Processing Architectures
Symmetric Multiprocessors
A Mainframe SMP
Switched interconnection
Shared L2 caches
Organization
Time shared or common bus
Multiport memory
Central control unit
Multiprocessor Operating System Design Considerations
Multiple Processor Organizations
Types of Parallel Processor Systems
Single instruction, multiple data (SIMD) stream
Single instruction, single data (SISD) stream
Multiple instruction, multiple data (MIMD) stream
Multiple instruction, single data (MISD) stream
Parallel Organizations
MIMD Distributed Memory
Loosely Coupled - Clusters
SISD
IS = instruction
MU = memory unit
DS = data
CU = control unit
PU = processing unit
MIMD Shared Memory
Tightly Coupled - NUMA
Tightly Coupled - SMP
SIMD
Cache Coherence and the Mesi Protocol
The MESI Protocol
Read hit
Read miss
Write miss
L1 - L2 cache consistency
Write hit
Write back
Write through
Hardware Solutions
Directory protocols
Write update
Write invalidate
Snoopy protocols
Write invalidate
Modified
Exclusive
Shared
Invalid
Write update
Nonuniform Memory Access
Motivation
Organization
NUMA Pros and Cons
Clusters
Clusters Compared to SMP
Cluster Configurations
Blade Servers
Operating System Design Issues
Failure management
Parallelizing computation
Parallelizing compiler
Parallelized application
Parametric computing
Load balancing
Single job-management system
Single I/O space
Single file hierarchy
Single process space
Single entry point
Checkpointing
Single control point
Process migration
Single memory space
Single user interface
Multithreading and Chip Multiprocessors
Implicit and Explicit Multithreading
Example Systems
Pentium 4
IBM Power 5
Approaches to Explicit Multithreading
Scalar variants
Single-threaded scalar
Interleaved multithreaded scalar
Blocked multithreaded scalar
Superscalar variants
Chip multiprocessing
Simultaneous (SMT)
Nonuniform Memory Access
Motivation
Organization
NUMA Pros and Cons