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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
RISC versus CISC Controversy
Quantitative
Problems
No pair of RISC and CISC that are directly comparable
No definitive set of test programs
Difficult to separate hardware effects from complier effects
Most comparisons done on “toy” rather than production machines
Most commercial devices are a mixture
Qualitative
Examins issues such as high-level language support and optimum use of VLSI real estate
Compiler-Based Register Optimization
Graph coloring approach
Edges
Nodes
MIPS R4000
Instruction Set
Instruction Pipeline
Instruction execute
Data cache first
Register file
Data cache second
Instruction fetch second half
Tag check
Instruction fetch first half
Write back
Risc Pipelining
Optimization of Pipelining
Delayed load
Loop unrolling
Delayed branch
Optimized delayed branch
Pipelining with Regular Instructions
Register to register instructions
I = Instruction Fetch
I = Instruction Fetch
Load and store operations
E: Execute. Calculates memory address
I: Instruction fetch.
D: Memory. Register-to-memory or memory-to-register operation
Instruction Execution Characteristics
Implications
Operands
Local scalar variables
Procedure Calls
Local variables
Operations
Assignments
Conditional statements (IF, LOOP)
Reduced Instruction Set Architecture
CISC versus RISC Characteristics
RISC Characteristics
Ability to take good advantage of compilers
Ease or difficulty of pipelining
Instruction decode complexity
Why CISC?
Characteristics of Reduced Instruction Set Architectures
Simple instruction formats
Hardwired design (no microcode)
Simple addressing modes
Fixed instruction format
Register-to-register operations
One instruction per cycle
The Use of a Large Register File
Local Variables Register
Large Register File versus Cache
Large Register File
Compiler-assigned global variables
Save/Restore based on procedure nesting depth
Individual variables
Register addressing
All local scalars
Blocks of memory
Blocks of memory
Recently-used local scalars
Save/Restore based on cache replacement algorithm
Memory addressing
Solution
Software solution
Hardware solution
Register Windows
Circular buffer - register windows
Overlapping register windows
Global Variables
SPARC
Instruction Set
Instruction Set
Shift Instructions
Load/Store Instructions
Arithmetic Instructions
Jump/Branch Instructions
Boolean Instructions
Miscellaneous Instructions
SPARC Register Set