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PROCESSOR STRUCTURE AND FUNCTION, Five-stage pipeline - Coggle Diagram
PROCESSOR STRUCTURE
AND FUNCTION
The x86 Processor Family
Register Organization
Eflags Register
Direction flag (DF)
I/O privilege flag (IOPL)
Interrupt enable flag (IF)
Resume flag (RF)
Trap flag (TF)
Alignment check (AC)
Identification flag (ID)
Control Registers
CR0 Register contain flags
Numeric Error (NE)
Write Protect (WP)
Extension Type (ET)
Alignment Mask (AM)
Task Switched (TS)
Not Write Through (NW)
Emulation (EM)
Cacje Disable (CD)
Monitor Coprocessor (MP)
Paging (PG)
Protection Enable (PE)
Types
Instruction Pointer
Numeric
Flags
Control
Segment
Status
General
Tag Word
MMX Registers
Interrupt Processing
Interrupt Vector Table
Interrupt Handling
A transfer to an interrupt-handling routine uses the system stack to store the processor state
Interrupts and Exceptions
Interupts
Maskable interrupts
Nonmaskable Interrupts
Exceptions
Processor-detected exceptions
Programmed exceptions
The ARM Processor
Processor Modes
The remaining six execution modes are referred to as privileged modes
Privilage modes
Exception Modes
System Mode
Exception Modes
Abort mode
Undefined mode
Supervisor mode
Fast interrupt mode
Interrupt mode
ARM architecture supports seven execution modes. Most application programs execute in user mode
Register Organization
General-purpose registers
Program status registers
CSPR contain user flags visible in user mode
Q flag
J bit
Condition code flags
GE[3:0] bits
CPSR contain system control flags
Interrupt disable bits
T bit
E bit
Mode bits
Processor Organization
Interrupt Processing
If more than one interrupt is outstanding, they are handled in priority order
When an exception occurs, the processor halts execution after the current instruction
Atributes
Flexibility: shifts/rotation using separate ALU and shifter units
Addressing Modes: small number, all determined from registers and instruction fields
Instruction Length: 32 bits (standard), 16 bits (Thumb)
Memory Access: indirect or indexed addressing not used
Data Processing: load/store model
Addressing Improvement: auto-increment and auto-decrement modes
Registers: moderate
Register Organization
Control and Status Registers
Memory address register (MAR)
Memory buffer register (MBR)
Instruction register (IR)
Common fields or flags include
Carry
Equal
Zero
Overflow
Sign
Interrupt Enable/Disable
Supervisor
Program counter (PC)
Example Microprocessor Register Organizations
User-Visible Registers
Address
May be devoted to a particular addressing mode
Data
Used only to hold data
General purpose
Assigned to a variety of functions
Condition codes
Referred to as flags, bits set by the processor hardware
Instruction Pipelining
Pipeline Hazards
Data hazards
Write after read (RAW), or antidependency
Write after write (RAW), or output dependency
Read after write (RAW), or true dependency
Control hazards
Resource hazards
Dealing with Branches
Prefetch branch target
When a conditional branch is recognized, the target of the branch is prefetched
Multiple streams
Branch instructions may enter the pipeline (either stream) before the original branch decision is resolved
Can improve performance
Contention delays for access to the registers and to memory
Loop buffer
A small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence
Branch prediction
Predict never taken
Predict always taken
Predict by opcode
Taken/not taken switch
Branch history table
Delayed branch
Pipelining Performance
Intel 80486 Pipelining
Pipelining Strategy
New inputs are accepted at one before previously accepted inputs appear as outputs at the other end
Additional stages
Calculate operands (CO)
Fetch operands (FO)
Decode instruction (DI)
Execute instruction (EI)
Fetch instruction (FI)
Write operand (WO)
Processor Organization
Processor Requirements
fetch data
Reading data from memory or an I/O module
Process data
Performing some arithmetic or logical operation on data
Interpret instruction
Instruction is decoded
write data
Writing data to memory or an I/O module
Fetch instruction
Reads an instruction from memory
Instruction Cycle
The indirect cycle
When using indirect addressing in computer instructions, additional memory accesses are required, which can be thought of as an additional instruction stage
Data flow
The exact sequence of events during an instruction cycle in a computer processir depends on its design
Five-stage pipeline