Processor Structure and Function
Register Organization
Example Microprocessor Register Organizations
User-Visible Registers
Control and Status Registers
Data
Address
General purpose
Condition codes
Program counter (PC)
Instruction register (IR)
Memory address register (MAR)
Memory buffer register (MBR)
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Program Status Word
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Equal
Carry
Overflow
Interrupt Enable/Disable
Zero
Supervisor
Sign
Instruction Cycle
The Indirect Cycle
Data Flow
Indirect cycle
Interrupt cycle
Fetch cycle
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The x86 Processor Family
Register Organization
Interrupt Processing
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Types of registers
Instruction pointer
Numeric
Flags
Control
Segment
Status
General
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Control and status registers
MMX registers
EFLAGS register
Interrupt vector table
Interrupt handling
Interrupt vector table
Exceptions
Interrupts
Nonmaskable interrupts
Maskable interrupts
Processor-detected exceptions
Programmed exceptions
Class 1: Traps on the previous instruction
Class 2: External interrupts
Class 3: Faults from fetching next instruction
Class 4: Faults from decoding the next instruction
Class 5: Faults on executing an instruction
Processor Organization
Process data
Write data
Fetch data
Interpret instruction
Small internal memory
Fetch instruction
The ARM Processor
Interrupt Processing
Register Organization
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Processor Organization
Processor Modes
Exception modes
Undefined mode
Fast interrupt mode
Abort mode
Interrupt mode
Supervisor mode
General-purpose registers
Program status registers