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Control Unit - Coggle Diagram
Control Unit
Micro-Operations
The Fetch Cycle
Memory address register (MAR)
Memory buffer register (MBR)
Program counter (PC)
Instruction register (IR)
First time unit
Second time unit
Third time unit
The Indirect Cycle
The Interrupt Cycle
The Execute Cycle
The Instruction Cycle
00: Fetch
01: Indirect
10: Execute
11: Interrupt
Control of the Processor
Functional Requirements
ALU
Registers
Internal data paths
External data paths
Control unit
Sequencing
Execution
Control Signals
Input
Clock
Instruction register
Flags
Control signals from control bus
Output
Control signals within the processor
Control signals to control bus
A Control Signals Example
Data paths
ALU
System bus
Internal Processor Organization
The Intel 8085
Incrementer/decrementer address latch
Interrupt control
Serial I/O control
Hardwired Implementation
Control Unit Inputs
Control Unit Logic
Hardwired implementation
Microprogrammed implementation