CONTROL UNIT OPERATION

Micro Operations

The Interrupt Cycle

The Execute Cycle (ADD)

The Indirect Cycle

The Instruction Cycle

The Fetch Cycle

Control of the Processor

A Control Signals Example

Internal Processor

Control Signals

Organization The Intel 8085

Functional Requirements

Hardwired Implementationigital Marketing

Control Unit Inputs

Control Unit Logic

Overview

Superscalar vs Superpipelined

Limitations

Procedural dependency

Resource conflicts

Output dependency

True data dependency

Antidependency

Superscalar

Superpipelined

Procedural dependencies

Resource conflict

Instruction issue policy

In-order issue with in-order completion

In-order issue with out-of-order completion

Out-of-order issue with out-of-order completion

Instruction are executed

Instruction are fetched

Instruction update the contents of register and memory locations

11 requires two cycles to execute

15 depends on the value produced by 14

15 and 16 conflict for a functional unit

13 and 14 conflict for the same functional unit

True Data Dependency

Procedural Dendencies

Resource Conflict

Reorder Buffer Simulator

Machine Parallelism

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Pipeline with Static Vs Dynamic Scheduling - Simulator

Branch Prediction

Superscalar Execution

Superscalar Implementation

Pentium 4

Generation of Micro-Ops

Trace Cache Next Instruction Pointer

Trace Cache Fetch

Out-of-Order Execution Logic

Allocate

Micro-Op Queuing

Micro-Op Scheduling and Dispatching

Integer and Floating-Point Execution Units

ARM Cortex-A8

Instruction Fetch Unit

Instruction Decode Unit

Integer Execute Unit

SIMD and Floating-Point Pipeline

Fetch - 4 Register

What happens when an instruction is executed?

Fetch Sequence (symbolic)

Varian 1

Varian 2

t2: MBR <- (memory) PC <- (PC) + 1

t3: IR <- (MBR)

t1: MAR <- (PC)

t2: MBR <- (memory)

t3: PC <- (PC) + 1 IR <- (MBR)

The Execute Cycle (ISZ)

MBR

MAR

Rules for clock cycle grouping

Conflicts must be avoided

Also: PC <- (PC) + 1 involves addition

Proper sequence must be followed

MAR <- (PC) must precede MBR <- (memory)

Musr not read & write same register at same time

MBR <- (memory) & IR <- (MBR) must not be in same cycle

Use ALU

May need additional micro-operations

Different for each instruction

E.g. ADD R1, X

ISZ X

MBR contains an address

IR is now in same state as if direct addressing had been used

Steps

MBR <- (memory)

MAR <- (IRaddress) - address field of IR

IRaddress <- (MBRaddress)

Execute Cycle (BSA)

BSA X

For a bigger picture, we need to tie sequences together

Assume new 2-bit register

Previous slides, we saw

Constituent Elements of Program Execution

Fetch Sequence

Result (data from memory) appears on data bus

Data from data bus copied into MBR

Control unit issues READ command

PC incremented by 1 (in parallel with data fetch from memory)

Address (MAR) is placed on address bus

data (instruction) moved from MBR to IR

MBR is now free for further data fetches

Address of next instruction is in PC