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Control Unit Operation - Coggle Diagram
Control Unit Operation
Micro-Operations
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Types
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Fetch sequence
Steps
Address of next instruction is in PC -> MAR is placed on address bus -> Control unit issues READ command -> Data from memory appears on data bus -> Data from data bus copied into MBR -> PC incremented by 1 -> Data moved from MBR to IR -> MBR is now free for further data fetches -> Repeat
Indirect cycle
Steps
MAR <- (IR address), MAR <- (IR address), IR address <- (MBR address)
Interrupt Cycle
Steps
t1: MBR <- (PC), t2: MAR <- save-address [somewhere in stack] & PC <- routine-address [interrupt handler], t3: memory <- (MBR)
Execute Cycle (ADD)
Steps
MAR <- (IR address), MBR <- (memory), R1 <- R1 + (MBR)
Execute Cycle (ISZ)
Steps
MAR <- (IR address), MBR <- (memory), MBR <- (MBR) + 1, memory <- (MBR), IF (MBR) == 0 then PC <- (PC) + 1
Execute Cycle (BSA)
Steps
t1: MAR <- (IR address) & MBR <- (PC), t2: PC <- (IR address) & memory <- (MBR), t3: PC <- (PC) + 1
Instruction Cycle
Steps
Codes
00: Fetch, 01: Indirect, 10: Execute, 11: Interrupt
Hardwired Implementation
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In hardwired implementation, input signals will be transformed to output signals. Control unit will also act as a state machine circuit
Control of the Processor
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Characterize
Steps
Define basic elements of processor, Describe micro-operations processor performs, Determine functions control unit must perform
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