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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
Major Advances in Computers
Cache memory
IBM S/360 model 85 1969
Solid State RAM
IBM S/360 model 85 1969
Microprogrammed control unit
Idea by Wilkes 1951, Produced by IBM S/360 1964
Microprocessors
Intel 4004 1971
The family concept
IBM System/360 1964, DEC PDP-8, Separates architecture from implementation
Pipelining
Introduces parallelism into fetch execute cycle
Multiple processors
CISC
Intention of CISC
Improve execution efficiency
Ease compiler writing
Support more complex HLLs
Driving force for CISC
Software costs far exceed hardware costs
Remember Moore’s Law
Increasingly complex high level languages
Semantic gap
Gap between language that human understands and computer understands
Inefficient program
Leads to
More addressing modes
Hardware implementations of HLL statements
Large instruction sets
Why CISC
Smaller programs
Compiler simplification
Faster programs
RISC
RISC Characteristics
Register to register operations
Few, simple addressing modes
One instruction per cycle
Few, simple instruction formats
Fixed instruction format
Hardwired design (no microcode)
More compile time/effort
Key features
Large number of general purpose registers
Use of compiler technology to optimize register use
Limited and simple instruction set
Emphasis on optimizing the instruction pipeline
Instruction execution characteristics
Operations
Assignment
Conditional statement
Operands
Optimisation should concentrate on accessing
local variables
Procedure Calls
Most programs do not do a lot of calls followed
by lots of returns
Most variables are local
Very time consuming
Implications
Best support is given by optimizing most used
and most time consuming features
Large number of register
Careful design of pipelines
Simplified (reduced) instruction set
Large Register File
Global Variables
Allocated by the compiler to memory
Have a set of registers for global variables
Register Windows
Function calls only uses few parameters
limited range of depth of call
Use multiple small sets of registers
Large Register File vs Cache
Hardware solution
Have more registers, thus more variables will be in registers
Software solution
Allocate based on most used variables in a given time
Requires sophisticated program analysis
Require compiler to allocate registers
Register is the fastest memory element, closest to or even part of the CPU
Compiler-Based Register Optimization
HLL programs have no explicit references to
registers
Map (unlimited) symbolic registers to real
registers
Optimizing use is up to compiler
Symbolic registers that do not overlap can share
real registers
Assume small number of registers (16-32)
Graph Coloring
Risc Pipelining
Pipelining with Regular Instructions
Optimization of Pipelining
Loop Unrolling
Reduces loop overhead
Increases instruction parallelism
Iterate loop fewer times
Improved register, data cache or TLB locality
Replicate body of loop a number of times
Delayed Load
Start the load, but processor idle until load complete
Continue execution of instruction stream until register required
Register to be target is locked by processor
Re-arranging instructions can allow useful work whilst loading
Compiler dependent
Most instructions are register to register
Two phases execution
Instruction fetch
Execute
load and store
Execute
Calculate memory address
Memory
Register to memory or memory to register operation
Instruction fetch
Controversy
Qualitative
Examines issues such as high-level language support and optimum use of VLSI real estate
Problems
Difficult to separate hardware effects from complier effects
Most comparisons done on “toy” rather than production machines
No definitive set of test programs
Most commercial devices are a mixture
No pair of RISC and CISC that are directly comparable
Quantitative
Attempts to compare program size and execution speed of programs on RISC and CISC machines that use comparable technology