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Processor Structure and Function - Coggle Diagram
Processor Structure and Function
Processor organization
Fetch data
The execution of an instruction may require reading data from memory or an I/O module
Process data
The execution of an instruction may require performing some arithmetic or logical operation on data
Interpret instruction
The instruction is decoded to determine what action is required
Write data
The results of an execution may require writing data to memory or an I/O module
Fetch instruction
The processor reads an instruction from memory (register, cache, main memory)
In order to do these things the processor needs to store some data temporarily and therefore needs a small internal memory
Instruction cycle
The indirect cycle
May involve one or more operands in memory, each of which requires a memory access
Data flow
Data flow refers to the movement and transformation of data in a computer system, particularly between the processor, memory, and I/O devices.
Reading and writing data to memory
Transferring data between registers
Processing data through arithmetic and logical operations
Fetch
Read the next instruction from memory into the processor
Execute
Interpret the opcode and perform the indicated operation
Interrupt
If interrupts are enabled and an interrupt has occurred, save the current process state and service the interrupt
The x86 processor family
Register organization
Register Organization
Instruction pointer
Numeric
Flags
Control
Segment
Status
Tag word
General
EFLAGS REGISTER
I/O privilege flag (IOPL)
Resume flag (RF)
Direction flag (DF)
Alignment check (AC)
Interrupt enable flag (IF)
Identification flag (ID)
Trap flag (TF)
CONTROL REGISTERS
x86 employs four control registers (register CR1 is unused) to control various aspects of processor operation
MMX REGISTERS
MMX instructions make use of 3-bit register address fields, so that eight MMX registers are supported
Interrupt processing
INTERRUPTS AND EXCEPTIONS
interrupt : generated by
a signal from hardware,and it may occur at random times during the execution of a
program
exception: generated from software, and it is provoked by the execution
of an instruction
INTERRUPT VECTOR TABLE
INTERRUPT HANDLING
To return from an interrupt, the interrupt service routine executes an IRET instruction
Instruction pipelining
Pipeline hazards
occurs when the pipelin stall because conditions do not permit continued execution
RESOURCE HAZARDS
occurs when two (or more) instructions
need the same resource
DATA HAZARDS
occurs when there is a conflict in the access of an
operand location
CONTROL HAZARDS
occurs when pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded
Dealing with branches
MULTIPLE STREAMS
PREFETCH BRANCH TARGET
LOOP BUFFER
Pipeline performance
Intel 80486 pipelining
Decode stage 1
Decode stage 2
Fetch
Execute
Write back
Pipelining strategy
two stages
fetches
execute
Additional Stages
Fetch instruction (FI)
Read the next expected instruction into a buffer
Decode instruction (DI)
Determine the opcode and the operand specifiers
Calculate operands (CO)
Calculate the effective address of each source operand
Fetch operands (FO)
Fetch each operand from memory, Operands in registers need not be fetched
Execute instruction (EI)
Perform the indicated operation and store the result, if any, in the specified destination operand location
Write operand (WO)
Store the result in memory
Register organization
User-visible registers
Enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers
General purpose
Can be assigned to a variety of functions by
the programmer
Data
May be used only to hold data and cannot be employed in the calculation of an operand address.
Address
May be somewhat general purpose or may be devoted to a particular addressing mode
Condition codes
Also referred to as flags, Bits set by the processor hardware as the result of operations
Control and status registers
Used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs
Program counter (PC)
Instruction register (IR)
Memory address register (MAR)
Memory buffer register (MBR)
Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.
Program Status Word (PSW)
Register or set of registers that contain status information
Sign
Zero
Carry
Equal
Overflow
Interrupt Enable/Disable
Supervisor
The Arm processor
Processor modes
User mode
Privileged modes
Exception Modes
Undefined mode
Fast interrupt mode
Abort mode
Interrupt mode
Supervisor mode
System mode
Register organization
Registers are organized into different banks for different processor modes
GENERAL-PURPOSE REGISTERS
PROGRAM STATUS REGISTERS
Processor organization
ARM is primarily a RISC system
Moderate array of uniform registers
A load/store model of data processing in which operations only perform on operands in registers and not directly in memory
A uniform fixed-length instruction of 32 bits for the standard set and 16 bits for the Thumb instruction set
Separate arithmetic logic unit (ALU) and shifter units
A small number of addressing modes with all load/store addresses
determined from registers and instruction fields
Auto-increment and auto-decrement addressing modes are used to improve the operation of program loops
Conditional execution of instructions minimizes the need for conditional branch instructions, thereby improving pipeline efficiency, because pipeline flushing is reduced
Interrupt processing
ARM processors handle two types of interrupts: IRQ (normal) and FIQ (fast). When an interrupt occurs, the processor switches to an appropriate mode (IRQ or FIQ), saves the current PC and CPSR into the corresponding SPSR and Link Register (LR), and jumps to the interrupt vector address to execute the interrupt service routine. Once the routine is completed, the processor restores the original state and resumes normal execution.