Please enable JavaScript.
Coggle requires JavaScript to display documents.
Instruction Sets: Addressing Modes and Formats - Coggle Diagram
Instruction Sets:
Addressing Modes and Formats
Instruction Format
Instruction Length
Affected by and affects
Memory organization
Bus structure
Memory size
CPU complexity
CPU speed
Trade off between powerful instruction repertoire and saving space
Allocation of Bits
determining factor
Register versus memory
Number of register sets
Number of operands
Address range
Number of addressing modes
Address granularity
two historical machine designs balance thefactors.
PDP-8
Simplest instruction designs
3 groups of OPR instructions
In group 2, the bit at 0400 is always 1
and the bit at 0001 is always 0.
In group 3, the bits at both 0400 and
0001 are always 1.
In group 1, the bit at 0400 (octal) is
always 0.
PDP-10
design principles
Completeness
Direct addressing
Orthogonality
designed to be a large-scale time-shared system
system easy to be proggammed
Variable-Length Instructions
PDP-11
was designed to provide a powerful and flexible instruction
set within the constraints of a 16-bit minicomputer
instructions are usually one word (16 bits) long
employs a set of eight 16-bit general-purpose registers
instruction set and addressing capability are complex
VAX
two criteria
All instructions should have the “natural” number of operands
. All operands should have the same generality in specification
Addressing Modes
Register
Operand is held in register named in
address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or
compiler writing
N.B. C programming
register int a;
with Direct addressing
Register Indirect
Operand is in memory cell pointed to by contents of register R
EA = (R)
indirect addressing
Large address space (2^n)
One fewer memory access than indirect addressing
Indirect
Memory cell pointed to by address field contains the address of (pointer to) the operand.
The processor first retrieves the address from the specified location and then accesses the operand in memory.
Large address space
2n where n = word length
May be nested, multilevel, cascaded
Virtual memory management
Symbolic or relocatable addressing
Dynamic data structures
EA = (((A)))
A = Value from instruction or register
((A)) = Memory[Memory[A]]
(((A))) = Memory[Memory[Memory[A]]]
EA = (((A)))
Multiple memory accesses to find operand
Displacement (Indexed)
EA = A + (R)
put simply, some fixed value + some 'changing' value
Address field hold two values
R = register that holds displacement
or vice versa
A = base value
common displacement addressing modes
Relative Addressing
A version of displacement addressing
EA = A + (PC)
R = Program counter, PC
locality of reference & cache usage
Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
EA = R + A
Very similar to relative addressing except that any register is used instead of PC
Indexed Addressing
EA = A + R
Good for accessing arrays
EA = A + (R)
R++
R = displacement
A = base
Direct
Address field contains address of operand
Effective address (EA) = address field (A)
Single memory reference to access data
No additional calculations to work out
effective address
Limited address space
Stack
Operand is (implicitly) on top of stack
Immediate
No memory reference to fetch data
Fast
Operand = address field
Limited range
Operand is part of instruction
Combinations
Indirect and indexing combined
Post-index
Pre-index
x86 and ARM Addressing Modes
x86 Addressing Modes
Virtual or effective address is offset into segment
Starting address plus offset gives linear address
This goes through page translation if paging enabled
ARM Addressing Modes
Only instructions that reference memory
Indirectly through base register plus offset
Three variants
Offset
Offset added to or subtracted from base register contents to form
the memory address
Preindex
Memory address is formed as for offset addressing
Memory address also written back to base register
So base register value incremented or decremented by offset value
like ++i in C
Postindex
Memory address is base register value
Offset added or subtracted
Result written back to base register
like i++ in C
Base register acts as index register for preindex and postindex addressing
Offset is either immediate value in instruction or another register
If scaled register addressing available
Offset register value scaled by shift operator
Instruction specifies shift size
Assembly Language
four instructions
Load the contents of location 201 into the AC.
Add the contents of location 202 to the AC.
Add the contents of location 203 to the AC.
.Store the contents of the AC in location 204
use a symbolic program
use symbolic addresses
programs are translated into machine language by an
assembler
x86 and ARM Instruction Formats
x86 Instruction Formats
the addressing mode is provided
The x86 format allows the use of not only 1-byte, but also 2-byte and 4-byte offsets for indexing
x86 instruction set is very complex
ARM Instruction Formats
Immediate Contants
THUMB INSTRUCTION SET
Increases performance in 16-bit or less
data bus
Re-encoded subset of ARM instruction set
Unconditional
Always update conditional flags
Subset of instructions