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Parallel Processing - Coggle Diagram
Parallel Processing
Design Issues
Instruction-Level Parallelism and Machine Parallelism
Instruction Issue Policy
instruction issue
The order in which instructions are fetched
The order in which instructions are executed
The order in which instructions update the contents of register and memory locations
instruction issue policy
In-order issue with in-order completion
In-order issue with out-of-order completion
Out-of-order issue with out-of-order completion
Register Renaming
Machine Parallelism
Branch Prediction
Superscalar Execution
Superscalar Implementation
Arm Cortex-A8
Instruction Fetch Unit
Instruction Decode Unit
Integer Execute Unit
SIMD and Floating-Point Pipeline
PENTIUM 4
Front End
GENERATION OF MICRO-OPS
TRACE CACHE NEXT INSTRUCTION POINTER
TRACE CACHE FETCH
DRIVE
Out-of-Order Execution Logic
ALLOCATE
State
Memory Address
Micro-op
Alias Register
REGISTER RENAMING
MICRO-OP QUEUING
MICRO-OP SCHEDULING AND DISPATCHING
Integer and Floating-Point Execution Units
Overview
Superscalar versus Superpipelined
Limitations
True data dependency
Procedural dependency
Resource conflicts
Output dependency
Antidependency