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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
Major Advances in Computers
Solid State RAM
Microprocessors
Cache memory
Pipelining
Microprogrammed control unit
Multiple processors
The family concept
RISC(Reduced Instruction Set Computer)
or use of compiler technology to optimize register use
Limited and simple instruction set
Large number of general purpose registers
Emphasis on optimising the instruction pipeline
CISC
Increasingly complex high level languages
Semantic gap
Software costs far exceed hardware costs
Semantic gap
More addressing modes
Hardware implementations of HLL statements
Large instruction sets
Intention of CISC
Improve execution efficiency
Support more complex HLLs
Ease compiler writing
Execution Characteristics
Operands used
Execution sequencing
Operations performed
operations dominates program
Assignments : Movement of data
Conditional statements (IF, LOOP) :Sequence control
Operands
Mainly local scalar variables
Optimisation should concentrate on accessing
local variables
Optimisation should concentrate on accessing
local variables
Most programs do not do a lot of calls followed
by lots of returns
Most variables are local
Very time consuming
Implications
Large number of registers
Careful design of pipelines
Best support is given by optimizing most used
and most time consuming features
Simplified (reduced) instruction set
Large Register File
Software solution
Allocate based on most used variables in a given time
Requires sophisticated program analysis
Require compiler to allocate registers
Hardware solution
Have more registers
Thus more variables will be in registers
Registers for Local Variables
Every procedure (function) call changes locality
Parameters must be passed
Reduces memory access
Results must be returned
Store local scalar variables in registers
Variables from calling programs must be restored
Optimization of Pipelining
Delayed Load
Loop Unrolling
Register Windows
Overlapping Register Windows
Circular Buffer
Register Windows cont.
Global Variables
Compiler Based Register Optimization
HLL programs have no explicit references to
registers
For each program, list possible variable
candidates which can be register
Optimizing use is up to compiler
Assign these candidates into a symbolic / virtual
register
Assume small number of registers (16-32)
Symbolic registers that do not overlap can share
real registers
If you run out of real registers some variables
use memory
Map (unlimited) symbolic registers to real
registers
Optimization task ➔ determine which variable
can be assigned to real register
RISC Characteristics
Few, simple instruction formats
Hardwired design (no microcode)
Few, simple addressing modes
Fixed instruction format
Register to register operations
More compile time/effort
One instruction per cycle
RISC Pipelining
Two phases of execution
For load and store
Delayed
branch
Shorter time for same execution sequence and result
Depends on the compiler
Controversy
Quantitative
Qualitative