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Control Unit - Coggle Diagram
Control Unit
Micro-operations
Fetch
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Fetch Sequence
Address of next instruction is in PC
Address (MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on data bus
Data from data bus copied into MBR
PC incremented by 1 (in parallel with data fetch from memory)
Data (instruction) moved from MBR to IR
MBR is now free for further data fetches
Symbolic
Variant 1
t1: MAR <- (PC)
t2: MBR <- (memory)
PC <- (PC) +1
t3: IR <- (MBR)
variant 2
t1: MAR <- (PC)
t2: MBR <- (memory)
t3: PC <- (PC) +1
IR <- (MBR)
Indirect Cycle
Steps
MAR <- (IRaddress) - address field of IR
MBR <- (memory)
IRaddress <- (MBRaddress)
MBR contains an address
IR is now in same state as if direct addressing had been
used
Interrupt Cycle
Steps
t1: MBR <-(PC)
t2: MAR <- save-address [somewhere in stack]
PC <- routine-address [interrupt handler]
t3: memory <- (MBR)
This is a minimum
May be additional micro-ops to get addresses
Execute Cycle (ADD)
Execute Cycle (ISZ)
Execute Cycle (BSA)
Control of the
Processor
Basic Elements
ALU
Registers
Internal data pahs
External data paths
Control Unit
Types of Micro-operation
Transfer data between registers
Transfer data from register to external
Transfer data from external to register
Perform arithmetic or logical ops
Control Unit
Control Signals
Clock
Instruction register
Flags
From control bus
Output
Within CPU
Via control bus
Hardwired
implementation
CU is a state machine circuit
Input signals transformed to output signals
Control unit inputs
Flags and control bus
Instruction register
Clock
Symbolize
Example Control Signal Sequence - Fetch
MAR <- (PC)
Control unit activates signal to open gates between PC
and MAR
MBR <- (memory)
Open gates between MAR and address bus
Memory read control signal
Open gates between data bus and MBR
