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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
Instruction Execution Characteristics
Operations
Assignment
Movement of data
Conditional statements (IF, LOOP)
Sequence control
Operands
Procedure Calls
Implications
Execution Characteristics
Operations performed
Operands used
Execution sequencing
Compiler-based register optimization
The Use of a Large Register File
Register Windows
Global Variables
Large Register File versus Cache
Reduced Instruction Set Architecture
Why CISC?
It is far from clear that CISC is the appropriate
solution
But we can’t say for clear that RISC is far better
than CISC
Characteristics of Reduced Instruction Set Architecture
One instruction per cycle
Register-to-register operations
Simple addressing modes
Simple instruction formats
CISC versus RISC Characteristics
RISC Pipelining
Pipelining with Regular Instructions
Two phases of execution
I: Instruction fetch
E: Execute
For load and store
I: Instruction fetch
E: Execute
D: Memory
Optimization of Pipelining
Delayed Branch
Delayed Load
Loop Unrolling
Can improve by
reducing loop overhead
increasing instruction parallelism by improving pipeline performance
improving register, data cache, or TLB locality
MIPS R4000
Instruction Set
Instruction Pipeline
Instruction fetch
Source operand fetch from register file
ALU operation or data operand address generation
Data memory reference
Write back into register file
SPARC
Instruction Ser
Instruction Format
SPARC Register Set
RISC Versus CISC Controversy
Quantitative
Attempts to compare program size and execution speed of programs on RISC and CISC machines that use comparable technology
Qualitative
Examins issues such as high-level language support and optimum
use of VLSI real estate