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REDUCED INSTRUCTION SET COMPUTERS, - Coggle Diagram
REDUCED INSTRUCTION
SET COMPUTERS
Risc Pipelining
Pipelining with regular instructions
Two phases of execution
Instruction fetch
Execute
For load and store
Instruction fetch
Execute
Memory
Most instructions are register to register
Effects of pipelining
Optimization of pipelining
Delayed load
Continue execution of instruction stream until register required
Start the load, but processor idle until load complete
Register to be target is locked by processor
Loop unrolling
Improve performance by:
Increasing instruction parallelism by improving pipeline performance
Improving register, data cache, or TLB locality
Reducing loop overhead
Delayed branch
Shorter time for same execution sequence and result
Depends on the compiler
Instruction Execution Characteristics
Operations
Two operations dominates program
Assignments: Movement of data
Conditional statements : Sequence control
Operands
Mainly local scalar variables
Optimisation should concentrate on accessing local variables
Execution Characteristics
Operands used
Execution sequencing
Operations performed
Procedure Calls
Very time consuming
Most programs do not do a lot of calls followed by lots of returns
Most variables are local
Intention of CISC
Improve execution efficiency
Ease compiler writing
Support more complex HLLs
Implications
Large number of register
Careful design of pipelines
Best support is given by optimizing most used and most time consuming features
Simplified (reduced) instruction set
MIPS R4000
Instruction Set
Data operations are register to register, with memory references limited to pure load/store operations.
Instruction Pipeline
Five pipeline stages of R3000
ALU operation or data operand address generation
Data memory reference
Source operand fetch from register file
Write back into register file
Instruction fetch
Eight pipeline stages of R4000
Instruction execute
Data cache first
Register file
Data cache second
Instruction fetch second half
Tag check
Instruction fetch first half
Write back
SPARC
Instruction Set
There are separateload and store instructions for word (32 bits), doubleword, halfword, and byte
The only available addressing mode, other than register, is displacement mode
Only simple load and store instructions reference memory
EA = (RS1) + S2 or EA = (RS1) + (RS2)
Available ALU operations
Bitwise Boolean AND, OR, XOR and their negations
Integer subtraction (with or without carry)
Integer addition (with or without carry)
Shift left logical, right logical, or right arithmetic
Instruction Format
The branch instruction includes a 4-bit condition field
The set instruction is a special instruction used to load or store a 32-bit value
SPARC uses a simple set of 32-bit instruction formats
SPARC Register Set
With the SPARC register architecture, it is usually not necessary to save andrestore registers for a procedure call
The compiler is simplified
The Use of a Large Register File
Global Variables
Allocated by the compiler to memory
Have a set of registers for global variables
Large Register File Versus Cache
Large Regiter File
Compiler-assigned global variables
Save/Restore based on procedure nesting depth
Individual variables
Register addressing
All local scalars
Cache
Recently-used local scalars
Blocks of memory
Recently-used global variables
Save/Restore based on cache nesting depth replacement algorithm
Memory addressing
Register Windows
Multiple small sets of registers
Three areas within a register set
Parameter registers
Local registers
Temporary registers
Limited range of depth of call
Temporary registers from one set overlap parameter registers from the next
Function calls only uses few parameters
Handles n-depth procedure calls
Compiler -Based Register Optimization
For each program, list possible variable candidates which can be register
Map (unlimited) symbolic registers to real registers
HLL programs have no explicit references to registers
Symbolic registers that do not overlap can share real registers
Optimizing use is up to compiler
Optimization task -> determine which variable can be assigned to real register
Reduced Instruction Set Architecture
Characteristics of Reduced Instruction Set Architectures
Few, simple instruction formats
Hardwired design (no microcode)
Few, simple addressing modes
Fixed instruction format
Register to register operations
More compile time/effort
One instruction per cycle
CISC versus RISC Characteristics
Not clear cut
Many designs borrow from both philosophies
Why CISC
CISC will yield smaller programs
Memory is now cheap
May not occupy less bits, just look shorter in symbolic form
Program takes up less memory
Faster programs
Bias towards use of simpler instructions in program
More complex control unit
Microprogram control store is also larger
Thus simple instructions take longer to execute
Compiler Simplification
Complex machine instructions harder to exploit
Disputed
Optimization more difficult
RISC versus CISC Controversy
Qualitative
Several problems
Quantitative