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Processor Structure and Function - Coggle Diagram
Processor Structure and Function
Processor Organization
Fetch data
Process data
Interpret instruction
Write data
Fetch instruction
Register Organization
Control and status registers
Instruction register(IR)
Memory address register(MAR)
Program counter(PC)
Memory buffer register(MBR)
User visible registers
Data
Address
Index registers
Stack pointer
Segment pointers
General purpose
Condition codes
Example microprocessor register organizations
Instruction Cycle
Execute
The indirect cycle
Data flow
Interrupt
The indirect cycle
Data flow
Fetch
Data flow
The indirect cycle
Instruction Pipelining
Pipelining strategy
Calculate operands (CO)
Fetch operands (FO)
Decode instruction (DI)
Execute instruction (EI)
Fetch instruction (FI)
Write operands (WO)
Pipeline performance
Pipeline hazards
Resource hazards
Data hazards
Write after read (RAW), or antidependency
Write after write (RAW), or output dependency
Read after write (RAW), or true dependency
Control hazards
Dealing with branches
Loop buffer
Branch prediction
Prefetch branch target
Delayed branch
Multiple streams
Intel 80486 pipelining
Decode stage 1
Decode stage 2
Fetch
Execute
Write back
The x86 Processor Family
Register organization
General
Segment
Flags
Instruction pointer
Numeric
Control
Status
Tag word
Interrupt processing
Exceptions
Interrupts
The ARM Processor
Processor organization
Processor modes
Undefined mode
Fast interrupt mode
Abort mode
Interrupt mode
Supervisor mode
Register organization
Program status
General purpose
Interrupt processing