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Processor Structure and Function - Coggle Diagram
Processor Structure and Function
Processor Requirements
Fetch instruction
The processor reads an instruction from memory (register, cache, main memory).
Interpret instruction
The instruction is decoded to determine what action is required.
Fetch data
The execution of an instruction may require reading data from memory or an I/O module
Process data
The execution of an instruction may require performing some arithmetic or logical operation on data.
Write data
The results of an execution may require writing data to memory or an I/O module.
Register Organization
User-visible registers
Enable the machine- or assembly language programmer to minimize main memory references by optimizing use of registers
Categories
General purpose
Can be assigned to a variety of functions by the programmer
Data
May be used only to hold data and cannot be employed in the calculation of an operand address
Address
May be somewhat general purpose or may be devoted to a particular addressing mode
Examples: segment pointers, index registers, stack pointer
Condition Codes
Also referred to as flags
Bits set by the processor hardware as the result of operations
Control and Status Registers
Program Status Word (PSW)
Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain privileged instructions can be executed only in supervisor mode, and certain areas of memory can be accessed only in supervisor mode
Interrupt Enable/Disable: Used to enable or disable interrupts.
Overflow: Used to indicate arithmetic overflow.
Equal: Set if a logical compare result is equality.
Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high-order bit. Used for multiword arithmetic operations.
Zero: Set when the result is 0.
Sign: Contains the sign bit of the result of the last arithmetic operation.
The PSW typically
contains condition codes plus other status information.
Four registers are essential to instruction execution
Memory buffer register (MBR): Contains a word of data to be written to
memory or the word most recently read
Memory address register (MAR): Contains the address of a location in memory
Instruction register (IR): Contains the instruction most recently fetched
Program counter (PC): Contains the address of an instruction to be fetched
Instruction Cycle
Fetch
Indirect
Execute
Interrupt
Instruction Pipelining
Additional Stages
Fetch instruction (FI): Read the next expected instruction into a buffer.
Decode instruction (DI): Determine the opcode and the operand specifiers.
Calculate operands (CO): Calculate the effective address of each source operand. This may involve displacement, register indirect, indirect, or other forms of address calculation.
Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be fetched.
Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified destination operand location.
Write operand (WO): Store the result in memory.
Data Hazard
Read after write (RAW), or true dependency
An instruction modifies a register or memory location
Succeeding instruction reads data in memory or register location
Hazard occurs if the read takes place before write operation is complete
Write after read (WAR), or antidependency
An instruction reads a register or memory location
Succeeding instruction writes to the location
Hazard occurs if the write operation completes before the read operation takes place
Write after write (WAW), or output dependency
Two instructions both write to the same location
Hazard occurs if the write operations take place in the reverse order of the intended sequence
Control Hazard
A control hazard, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.
Dealing with branches
Multiple Streams
A simple pipeline suffers a penalty for a branch instruction because it must choose one of two instructions to fetch next and may make the wrong
choice
Prefetch Branch Target When a conditional branch is recognized, the target
of the branch is prefetched, in addition to the instruction following the branch.
Loop Buffer
A loop buffer is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence.
Branch Prediction
Various techniques can be used to predict whether a branch will be taken.
Among the more common are the following:
Predict never taken
Predict always taken
Predict by opcode
Taken/not taken switch
Branch history table
