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PROCESSOR STRUCTURE AND FUNCTION - Coggle Diagram
PROCESSOR STRUCTURE
AND FUNCTION
Processor Organization
Processor Requirements
Fetch data
Process data
Interpret instruction
Fetch instruction
Write data
Instruction Pipelining
Pipeline Hazards
DATA HAZARDS
CONTROL HAZARDS
RESOURCE HAZARDS
Dealing with Branches
Loop buffer
Branch prediction
Prefetch branch target
Delayed branch
Multiple streams
Pipeline Performance
Intel 80486 Pipelining
Decode stage 1
Decode stage 2
Fetch
Execute
Write back
Pipelining Strategy
Additional Stages
Decode instruction (DI)
Calculate operands (CO)
Fetch instruction (FI)
Fetch operands (FO)
Execute instruction (EI)
Write operand (WO)
new inputs are accepted at one end before previously accepted
inputs appear as outputs at the other end
Instruction Cycle
Data Flow
the exact sequence of events during an instruction cycle in a
computer processor depends on its design
The Indirect Cycle
when using indirect addressing in computer instructions,additional memory accesses are required, which can be thought of as an additional instruction stage
The x86 Processor Family
Register Organization
EFLAGS REGISTER
Direction flag (DF)
I/O privilege flag (IOPL)
Interrupt enable flag (IF)
Resume flag (RF)
Trap flag (TF)
Alignment check (AC)
Identification flag (ID)
CONTROL REGISTERS
Types
Instruction Pointer
Numeric
Flags
Control
Segment
Status
General
Tag Word
MMX REGISTERS
Interrupt Processing
INTERRUPT VECTOR TABLE
INTERRUPT HANDLING
a transfer to an interrupt-handling routine uses the system
stackto store theprocessor state
Interrupts and Exceptions
Interupts
Maskable interrupts
Nonmaskable interrupts
Exceptions
Processor-detected exceptions
Programmed exceptions
The ARM Processor
Processor Modes
ARM architecture supports seven execution modes. Most
application programs execute in user mode
Exception Modes
The remaining six execution modes are referred to as privilege modes
Register Organization
General Purpose Registers
Program Status Register
Processor Organization
Interrupt Processing
If more than one interrupt is outstanding, they are handled in
priority order
When an exception occurs, the processor halts execution after the current instruction
Attributes
Addressing Modes: small number, all determined from registers
Memory Access: indirect or indexed addressing not used
Flexibility: shifts/rotations using separate ALU and shifter units
Instruction Length: 32 bits (standard), 16 bits (Thumb)
Data Processing: load/store model
Addressing Improvement: auto-increment and auto-decrement modes.
Registers: moderate
Register Organization
Control and Status Registers
Instruction register (IR)
Memory address register (MAR)
Program counter (PC)
Memory buffer register (MBR)
Common fields or flags include
Example Microprocessor Register Organizations
User-Visible Registers