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Chapter 14 - Control Unit - Coggle Diagram
Chapter 14 - Control Unit
Micro-Operation
The Fetch Cycle
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
The Indirect Cycle
The Interrupt Cycle
The Execute Cycle
The Instruction Cycle
Hardwired Implementation
Control Unit Inputs
Control Unit Logic
PQ = 01 Indirect Cycle
PQ = 10 Execute Cycle
PQ = 00 Fetch Cycle
PQ = 11 Interrupt Cycle
Control of the Processor
Functional Requirements
Sequencing
Execution
Control Signals
Input
Clock
Instruction Register
Flags
Control Signals from Control Bus
Output
Control Signals within the Processor
Control Signals to Control Bus
A Control Signals Example
Data Paths
ALU
System Bus
Internal Processor Organization
The Intel 8085
Interrupt Control
Serial I/O Control
Incrementer/Decrementer Address Latch