Please enable JavaScript.
Coggle requires JavaScript to display documents.
Chapter 13 - Parallel Processor - Coggle Diagram
Chapter 13 - Parallel Processor
Multithreading and Chip Multiprocessors
Implicit and Explicit Multithreading
Process
Resource Ownership
Scheduling/Execution
Process Switch
Thread
Thread Switch
Approaches to Explicit Multithreading
Interlaced Multithreading
Blocked Multithreading
Simultaneous Multithreading (SMT)
Chip Multiprocessing
Example Systems
IBM POWER5
Clusters
Cluster Configurations
Operating System Design Issues
Failure Management
Load Balancing
Parallelizing Computation
Parallelizing Compiler
Parallelized Application
Parametric Computing
Cluster Computer Architecture
Desirable Cluster Middleware Services and Functions
• Single entry point: A user logs onto the cluster rather than to an individual computer.
• Single file hierarchy: The user sees a single hierarchy of file directories under the same root directory.
• Single control point: There is a default workstation used for cluster management and control.
• Single virtual networking: Any node can access any other point in the cluster, even though the actual cluster configuration may consist of multiple intercon-nected networks. There is a single virtual network operation.
• Single memory space: Distributed shared memory enables programs to share variables.
• Single job-management system: Under a cluster job scheduler, a user can submit a job without specifying the host computer to execute the job.
• Single user interface: A common graphic interface supports all users, regardless of the workstation from which they enter the cluster.
• Single I/O space: Any node can remotely access any I/O peripheral or disk device without knowledge of its physical location.
• Single process space: A uniform process-identification scheme is used. A process on any node can create or communicate with any other process on a remote node.
• Checkpointing: This function periodically saves the process state and intermediate computing results, to allow rollback recovery after a failure.
• Process migration: This function enables load balancing.
Blade Servers
Clusters Compared to SMP
Symmetric Multiprocessors
Organization
Addressing
Arbitration
Time-Sharing
Simplicity
Flexibility
Rellability
Multiprocessor Operating System Design Considerations
Simultaneous Concurrent Process
Scheduling
Synchronization
Memory Management
Rellability and Fault Tolerance
A Mainframe SMP
Switched Interconnection
Shared L2 Caches
Multiple Processor Organizations
Types of Parallel Processor Systems
Multiple Instruction, Single Data (MISD) Stream
Multiple Instruction, Multiple Data (MIMD) Stream
Single Instruction, Multiple Data (SIMD) Stream
Single Instruction, Single Data (SISD) Stream
Parallel Organizations
Cache Coherence and The Mesi Protocol
Software Solutions
Hardware Solutions
Directory Protocols
Snoopy Protocols
The MESI Protocol
4 States
Modified
Exclusive
Shared
Invalid
Read Miss
Read Hit
Write Miss
Write Hit
Shared
Exclusive
Modified
L1-L2 Cache Consistency
Nonuniform
Uniform Memory Access (UMA)
Motivation
Organization
NUMA Pros and Cons
Nonuniform Memory Access (NUMA)
Cache-coherent NUMA (CC-NUMA)
Vector Computation
Approaches to Vector Computation
Pipelined ALU
Parallel ALUs
Parallel Processors
IBM 3090 Vector Facility
Organization
Registers
Compound Instructions