Please enable JavaScript.

Coggle requires JavaScript to display documents.

Chapter 12 - RISC - Coggle Diagram

- - - - Integer Addition
      - Integer Subtraction
      - Bitwise Boolean AND, OR, XOR and Their Negations
      - Shift Left Logical, Right Logical, or Right Aritmethic
- - - - One Instruction Per Cycle
      - Register To Register Operations
      - Simple Addressing Modes
      - Simple Instruction Formats
    - - Characteristics Of Classic RISC
        
        A single instruction size.
        
        That size is typically 4 bytes.
        
        A small number of data addressing modes, typically less than five.This parameter is difficult to pin down. In the table, register and literal modes are not counted and different formats with different offset sizes are counted separately.
        
        No indirect addressing that requires you to make one memory access to get the address of another operand in memory.
        
        No operations that combine load/store with arithmetic (e.g., add from memory, add to memory).
        
        No more than one memory-addressed operand per instruction.
        
        Does not support arbitrary alignment of data for load/store operations.
        
        Maximum number of uses of the memory management unit (MMU) for a data address in an instruction.
        
        Number of bits for integer register specifier equal to five or more. This means that at least 32 integer registers can be explicitly referenced at a time.
        
        Number of bits for floating-point register specifier equal to four or more.This means that at least 16 floating-point registers can be explicitly referenced at a time.