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Processor Structure and Function - Coggle Diagram
Processor Structure and Function
Processor Organization
Requirements
Fetch instruction
Interpret instruction
Fetch data
Process data
Write data
Small internal memory
Register Organization
Roles
User-Visible Registers
Enable assembly language, minimize main memory reference
Categories
General purpose
Data
Address
Condition codes
Control and Status Register
Program Counter (PC)
Instruction Register (IR)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Status Word (PSW)
Sign
Zero
Carry
Equal
Overflow
Interrupt Enable/Disable
Supervisor
Instruction Cycle
Diagram
Indirect Cycle
Access address that is not specified in the instruction
Data Flow
Between memory and register
Instruction Pipelining
Strategy
Similar to the use of an assembly line
Performance
Affected by clock speed, strategy, hazards, stages
Hazards
Pipeline must stall because conditions do not permit continued execution
Types
Resource
Two or more instructions
already in the pipeline and need the same resource
Data
Conflict in the access of the operand location
Control
Wrong decision on a branch prediction
Dealing with Branches
Multiple streams
Prefetch branch target
Looped buffer
Branch prediction
Delayed branch
Intel 80486 Pipelining
Fetch
Decode stage 1
Decode stage 2
Execute
Write back
x86 Processor Family
Register organization
General
Segment
Flags
Instruction Pointer
Numeric
Control
Status
Tag word
More complex registers:
EFLAGS
Control
MMX
Interrupt processing
Interrupts
Generated by hardware, may occur during program execution
Maskable
Nonmaskable
Execptions
Generated by software, provoked by an instruction
Processor detected
Programmed
Interrupt vector table
Interrupt is assigned a number to index into the interrupt vector table
ARM Processor
Processor organization
Based on ARM architecture versions
Processor modes
User
Supervisor
Abort
Undefined
Fast interrupt
Interrupt
Register organization
General purpose
Program status
Interrupt processing
Enables the processor to interrupt the currently executing program to deal with exception conditions