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Parallel Processing - Coggle Diagram

- - - - Addressing - distinguish modules on bus
      - Arbitration - any module can be temporary master
      - Time sharing - if one module has the bus, others
        must wait and may have to suspend
    - - Simplicity
        
        Structure similar to single processor system
      - Flexibility
        
        Easy to upgrade by adding more processors
      - Reliability
        
        The bus is passive medium, failure of any
        attached device should not cause failure of the whole system
    - - Performance limited by bus cycle time
      - Each processor should have local cache
      - Leads to problems with cache coherence
- - - - Resource ownership
      - Scheduling/execution
      - An instance of program running on computer
    - - Includes processor context (which includes the
        program counter and stack pointer) and data area for stack
      - Thread executes sequentially
      - Interruptible: processor can turn to another thread
  - - - concurrent execution of multiple threads extracted from single sequential program
      - Implicit threads defined statically by compiler or
        dynamically by hardware
    - - “Concurrently execute instructions” from different
        explicit threads
  - - - Issue multiple instructions at a time
      - One thread may fill all horizontal slots
      - Instructions from two or more threads may be issued
      - With enough threads, can issue maximum number of
        instructions on each cycle
    - - Multiple processors
        
        Each has two-issue superscalar processor
        
        Each processor is assigned thread
- - - - Vector processor
      - Array processor
      - About
        
        Single machine instruction
        
        Controls simultaneous execution
        
        Number of processing elements
        
        Lockstep basis
        
        Each processing element has associated
        data memory
        
        Each instruction executed on different set
        of data by different processors
        
        Vector and array processors
    - - Shared Memory (tightly coupled)
        
        Symmetric Multiprocessor (SMP)
        
        Characteristics
        
        Processors share same memory and I/O
        
        Processors are connected by a bus or other
        internal connection
        
        Memory access time is approximately the same for
        each processor
        
        All processors share access to I/O
        
        All processors can perform the same functions
        (hence symmetric)
        
        System controlled by integrated operating system
        
        Two or more similar processors of comparable
        capacity
        
        Advantages
        
        Performance
        
        If some work can be done in parallel
        
        Availability
        
        —Since all processors can perform the same functions, failure of a single processor does not halt the system
        
        Incremental growth
        
        User can enhance performance by adding
        additional processors
        
        Scaling
        
        Vendors can offer range of products based on
        number of processors
        
        Nonumiform Memory Access (NUMA)
        
        Access times to different regions of
        memory may differ
      - Distributed Memory (loosely coupled)
        
        Clusters
        
        Collection of independent uniprocessors or
        SMPs
        
        Communication via fixed path or network
        connections
      - About
        
        Set of general-purpose processors
        
        Simultaneously execute different instruction
        sequences
        
        Each can process all instructions necessary
        
        Different sets of data
        
        Further classified by method of processor
        communication
        
        SMPs, clusters and NUMA systems
        
        Symmetric multiprocessors
        
        Non-uniform memory access
    - - Uniprocessor
      - About
        
        Single processor
        
        Single instruction stream
        
        Data stored in single memory
        
        Uni-processor
    - - About
        
        Sequence of data
        
        Transmitted to set of processors
        
        Each processor executes different
        instruction sequence
        
        Never been implemented