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PROCESSOR STRUCTURE AND FUNCTION, five-stage pipeline - Coggle Diagram
PROCESSOR STRUCTURE
AND FUNCTION
Processor Organization
Processor Requirements
Fetch data
reading data from
memory or an I/O module.
Process data
performing some
arithmetic or logical operation on data
Interpret instruction
instruction is decoded
Write data
writing data to memory or
an I/O module
Fetch instruction
reads an instruction from memory
Instruction Cycle
The Indirect Cycle
the execution of an instruction may involve one or
more operands in memory, each of which requires a memory access.
Data Flow
during fetch, instruction is read from memory
address is moved to the MAR and placed on the address bus
The control unit requests a memory read
result is placed on the data bus
and copied into the MBR and then moved to the IR
Once the fetch cycle is over, the control unit examines the contents of the IR
to determine if it contains an operand specifier using indirect addressing
Instruction Pipelining
Pipeline Hazards
DATA HAZARDS
Write after read (WAR), or antidependency
Write after write (WAW), or output dependency:
Read after write (RAW), or true dependency
occurs when there is a conflict in the access of an
operand location
CONTROL HAZARDS
occurs when pipeline makes the wrong decision on a branch prediction
RESOURCE HAZARDS
occurs when two (or more) instructions
that are already in the pipeline need the same resource
result : the instructions must be executed in serial rather than parallel
occurs when the pipeline, or some portion of the pipeline,
must stall because conditions do not permit continued execution
Dealing with Branches
Loop buffer
a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline
and containing the n most recently fetched instructions, in sequence
BENEFITS
Instructions fetched in sequence will be available without the
usual memory access time
If a branch occurs to a target just a few locations ahead of the
address of the branch instruction, Target will already be in buffer
well suited to dealing with loops
Branch prediction
Predict by opcode
Taken/not taken switch
Predict always taken
Branch history table
Predict never taken
Prefetch branch target
When a conditional branch is recognized, the target
of the branch is prefetched
Target is then saved until the branch
instruction is executed
If the branch is taken, the target has already
been prefetched
Delayed branch
Multiple streams
contention delays for access to the registers
and to memory
branch instructions may enter the pipeline (either stream) before
the original branch decision is resolved
can improve performance
A simple pipeline suffers a penalty for a
branch instruction
Pipeline Performance
Intel 80486 Pipelining
Decode stage 2
Execute
Decode stage 1
Write back
Fetch
Pipelining Strategy
new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end
Additional Stages
Decode instruction (DI)
Calculate operands (CO)
Fetch instruction (FI)
Fetch operands (FO)
Execute instruction (EI)
Write operand (WO)
pipelining: laying the production process out in an assembly line products at various stages can be worked on simultaneously
The x86 Processor Family
Register Organization
Types
Control
Status
Numeric
Tag word
Instruction pointer
Segment
Flags
General
EFLAGS REGISTER
Direction flag (DF)
I/O privilege flag (IOPL)
Interrupt enable flag (IF)
Resume flag (RF)
Trap flag (TF)
Alignment check (AC)
Identification flag (ID)
CONTROL REGISTERS
CR0 Register contain flags
Task Switched (TS):
Extension Type (ET)
Emulation (EM)
Numeric Error (NE)
Monitor Coprocessor (MP):
Write Protect (WP)
Protection Enable (PE)
Alignment Mask (AM)
Not Write Through (NW)
Cache Disable (CD)
Paging (PG)
MMX REGISTERS
Interrupt Processing
Interrupts and Exceptions
Exceptions
Processor-detected exceptions
Programmed exceptions
generated from software
provoked by the execution
of an instruction
Interupts
Maskable interrupts
Nonmaskable interrupts
generated by
a signal from hardware
may occur at random times during the execution of a
program
INTERRUPT VECTOR TABLE
INTERRUPT HANDLING
a transfer to an interrupt-handling routine uses the system stackto store theprocessor state
Register Organization
Control and Status Registers
Instruction register (IR)
Memory address register (MAR)
Program counter (PC)
Memory buffer register (MBR)
Common fields or flags include
Zero
Carry
Equal
Overflow
Interrupt Enable/Disable
Supervisor
Sign
Example Microprocessor Register Organizations
User-Visible Registers
Data
used only to hold data
Address
may be devoted to a particular addressing mode
General purpose
assigned to a variety of functions
Condition codes
referred to as flags, bits set by the processor hardware
The ARM Processor
Processor Organization
Register Organization
GENERAL-PURPOSE REGISTERS
PROGRAM STATUS REGISTERS
CPSR contain user flags visible in User
mode
Q flag
J bit
Condition code flags
GE[3:0] bits
CPSR contain system control flags
Interrupt disable bits
T bit
E bit
Mode bits
Attributes
Flexibility: shifts/rotations using separate ALU and shifter units
Addressing Modes: small number, all determined from registers and instruction fields
Instruction Length: 32 bits (standard), 16 bits (Thumb)
Memory Access: indirect or indexed addressing not used
Data Processing: load/store model
Addressing Improvement: auto-increment and auto-decrement modes.
Registers: moderate
Interrupt Processing
If more than one interrupt is outstanding, they are handled in priority order
When an exception occurs, the processor halts execution after the current instruction
Processor Modes
ARM architecture supports seven execution modes. Most application programs execute in user mode
The remaining six execution modes are referred to as privileged modes
Privilage modes
Exception Modes
System Mode
Exception Modes
Supervisor mode
Abort mode
Undefined mode
Fast interrupt mode
Interrupt mode
five-stage pipeline