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Reduced Instruction Set Computers (RISC) - Coggle Diagram
Reduced Instruction Set Computers (RISC)
Instruction Execution Characteristics
Operations
Operands
Procedure Calls
Implications
The Use of a Larger Register File
Register Windows
Global Variables
Large Register File vs Cache
Compiler-Based Register Optimization
Reduced Instruction Set Architetecture
Why CISC?
Characteristics of Reduced Instruction Set Architectures
One instruction per cycle
Register-to-register operations
Simple addressing modes
Simple instruction formats
CISC versus RISC Characteristics
RISC Characteristics
Fixed instruction size (usually 4 bytes)
Small number of data addressing modes (usually less than 5)
No indirect addressing that requires an additional memory access
No load/store combined with arithmetic operations.
No more than one memory-addressed operand per instruction
Does not support arbitrary alignment of data for load/store operations
Maximum number of uses of the memory management unit (MMU) for a data address in an instruction
At least 32 integer registers can be explicitly referenced at a time
At least 16 floating-point registers can be explicitly referenced at a time
RISC Pipelining
Pipelining with Regular Instructions
Register to Register
I: Instruction fetch
E: Execute
Load and Store
D: Memory
E: Execute
I: Instruction fetch
Optimization of Pipelining
Delayed Branch
Delayed Load
Loop Unrolling
MIPS R4000
Instruction Set
Instruction Pipeline
Instruction fetch
Source operand fetch from register file
ALU operation or data operand address generation
Data memory reference
Write back into register file
SPARC
SPARC Register Set
Instruction Set
Instruction Format
RISC vs CISC Controversy
Quantitative
Attempts to compare program size and execution speed of programs on RISC and CISC machines that use comparable technology
Qualitative
Examins issues such as high-level language support and optimum use of VLSI real estate