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Instruction Sets: Addressing Modes and Formats, requires the instruction…
Instruction Sets:
Addressing Modes and Formats
Addressing
Register Addressing
Limited Number of registers
Advantages:
Very small address field needed
No memory access
Very fast execution
Operand is held in register named in
address filed, EA=A.
Disadvantages:Very limited address space
Register Indirect Addressing
Operand is in memory cell pointed to by
contents of register R
Large address space (2^n)
C.f. indirect addressing, EA = (R)
One fewer memory access than indirect
addressing
Indirect Addressing
Large address space
May be nested, multilevel, cascaded
Memory cell pointed to by address field contains the address of the operand, (EA) = address field (A)
Multiple memory accesses to find operand, hence slower
Displacement Addressing
A very powerful mode of addressing , EA = A + (R)
A = base value
R = register that holds displacement
Base-register addressing
EA = R + A.
Indexing
EA = A + R
combination
Post-index
EA = (A) + (R)
Pre-index
EA = (A+(R))
Relative addressing
EA = A + (PC)
three of the most common uses of displacement addressing
Direct Addressing
No additional calculations to work out
effective address
Limited address space
Address field contains address of operand, Effective address (EA) = address field (A)
Stack Addressing
sometimes referred to
pushdown list or last-in-first-out queue
Operand is (implicitly) on top of stack
Immediate Addressing
The simplest form of addressing, value is present in the instruction, Operand = address field
Limited range
No memory reference to fetch data, fast
Instruction Formats
Allocation of Bits
Number of addressing modes
Number of operands
Register versus memory
Number of register sets
Address range
Address granularity
PDP-8
3 groups of OPR instructions
In group 2, the bit at 0400 is always 1
and the bit at 0001 is always 0.
In group 3, the bits at both 0400 and
0001 are always 1.
In group 1, the bit at 0400 (octal) is
always 0
simplest instruction designs
ses 12-bit instructions and operates on
12-bit words
Each
memory reference consists of 7 bits plus two 1-bit modifiers
PDP-10
designed to be a large-scale time-shared system
design principles
Orthogonality
two variables are independent of each other.
Completeness
Each arithmetic data type (
should have a complete and identical set of operations.
Direct addressing
Base plus displacement addressing
Variable-Length Instructions
PDP-11
designed to provide a powerful and flexible instruction
set
employs a set of eight 16-bit general-purpose registers
instruction set and addressing capability are complex
instructions are usually one word (16 bits) long
VAX
criteria
Instructions should have the “natural” number of operands
operands should have the same generality in specification
Instruction Length
Affected by and affects
Bus structure
CPU complexity
Memory organization
CPU speed
Memory size
Trade off between powerful instruction
repertoire and saving space
x86 and ARM Instruction Format
x86 Instruction Format
the prefix bytes:
Opcode
ModR/m
Address size
SIB
Operand size
Displacement
Segment override
Immediate
Instruction prefixes
ARM Instruction Format
Immediate Constants
Thumbs Instruction Set
Increases performance in 16-bit or less
data bus
Unconditional (4 bits saved)
Always update conditional flags
Subset of instructions
2 bit opcode, 3 bit type field (1 bit saved)
Reduced operand specifications (9 bits saved)
x86 and ARM Addressing Modes
x86 Instruction Formats
Base with displacement
LA = (SR) + (B) + A
Scaled index with displacement
LA = (SR) + (I) * S + A
Base
LA = (SR) + (B)
Base with index and displacement
LA = (SR) + (B) + (I) + A
Displacement
LA = (SR) + A
Register operand
LA = R
Base with Scaled Index and Displacement
LA = (SR) + (I) * S + (B) + A
Immediate
Operand = A
Relative
LA = (PC) + A
ARM addressing modes
DATA PROCESSING INSTRUCTION ADDRESSING
BRANCH INSTRUCTIONS
LOAD/STORE ADDRESSING
Load and store instructions are the only instructions
that reference memory.
Done Indirectly through base register plus offset
Three Variants
Postindex
Memory address is base register value
Offset added or subtracted
Result written back to base register
Preindex
Memory address is formed as for offset addressing, also written back to base register
Offset
added to or subtracted from base register contents to form
the memory address
LOAD/STORE MULTIPLE ADDRESSING
assembly language
Machines store and understand binary
instructions
steps code
Load contents of 201 into AC
Add contents of 202 to AC
Add contents of 203 to AC
Store contents of AC to 204
use symbolic program and address
programs are translated into machine language by an
assembler
requires the instruction to have two address fields
two historical machine designs balance these various factors
factors that determine the
use of the addressing bits.