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Processor Structure and Function, Fetch, Stages - Coggle Diagram
Processor Structure and Function
Processor organization
Processor Requirements
Fetch instruction
Interpret instruction
Fetch data
Process data
Write data
Register organization
Roles
User-Visible Registers
Categories
Data
Address
General purpose
Condition codes
Control and Status Registers
Program counter (PC)
Instruction register (IR)
Memory address register (MAR)
Memory buffer register (MBR)
Instruction cycle
Data Flow
Indirect Cycle
The Arm processor
Processor organization
Processor modes
Register organization
Interrupt processing
The x86 processor family
Register organization
Interrupt processing
Interrupts and Exceptions
Interrupts
Exceptions
Interrupt vector table
Instruction pipelining
Pipelining strategy
Two-Stage Instruction Pipeline
Simplified view
Expanded view
Pipeline performance
Additional Stages
Fetch instruction (FI)
Decode instruction (DI)
Calculate operands (CO)
Fetch operands (FO)
Execute instruction (EI)
Write operand (WO)
Pipeline hazards
Types of Data Hazard
Read after write (RAW), or true dependency
Write after read (WAR), or antidependency
Write after write (WAW), or output dependency
Control Hazard
Also known as a branch hazard
Occurs when the pipeline makes the wrong decision on a branch prediction
Brings instructions into the pipeline that must subsequently be discarded
Dealing with Branches
Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch
Dealing with branches
Prefetch Branch Target
Loop Buffer
Branch Prediction
Intel 80486 pipelining
Fetch
Indirect
Execute
Interrupt
Stages