Addressing Modes

Immediate Addressing

Operand is part of instruction

Operand = address field

No memory reference to fetch data

Fast but limited range

Immediate Addressing Diagram image

Direct Addressing

Address field contains address of operand

Effective address (EA) = address field (A)

Single memory reference to access data

No additional calculations to work out
effective address

Limited Address Space

Direct Addressing Diagram image

Indirect Addressing

Memory cell pointed to by address field contains the address of (pointer to) the operand

Multiple memory accesses to find operand, Hence slower

Register Addressing

Limited number of registers

No memory access

Very fast execution

Register Indirect Addressing

Operand is in memory cell pointed to by
contents of register R

One fewer memory access than indirect
addressing

Displacement Addressing Diagram

Relative

Base-register

Indexing

Relative Addressing

get operand from A cells from current
location pointed to by PC (program counter)

Base-Register Addressing

Very similar to "Relative Addressing"except that any register is used instead of PC

Indexed Address

Combinations

Post-index

Pre-index

EA = (A) + (R)

EA = (A+(R))

Stack Addressing

Operand is (implicitly) on top of stack

Addressing Modes

x86 Addressing Modes

Virtual or effective address is offset into segment

Starting address plus offset gives linear address

This goes through page translation if paging enabled

ARM Addressing Modes Load/Store

Offset

Preindex

Postindex

added to or subtracted from base register contents to form
the memory address

++i

i++

ARM

Data Processing

Branch

Multiple Addressing

Register addressing

Immediate

Instruction contains 24 bit value

Instructions

Formats

Usually more than one instruction format
in an instruction set

Length

Memory size

Bus structure

CPU complexity

CPU speed

Memory organization

Allocation of Bits

Number of addressing modes

Number of register sets

Number of operands

PDP-8

PDP-10

PDP-11

x86

ARM

Thumb Instruction Set

Re-encoded subset of ARM instruction set

Increases performance in 16-bit or less
data bus

Assembler

Machines store and understand binary
instructions

Improvements

Use hexadecimal rather than binary

Symbolic Addresses

Now have assembly language and need an
assembler to translate