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Control Unit Operation - Coggle Diagram
Control Unit Operation
Micro-Operations
Atomic operations of the CPU
Fetch cycle
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Fetch sequence
Address of next instruction is in PC
MAR is placed on address bus
Control unit issues READ command
Data from memory appears on data bus
Data from data bus copied into MBR
PC incremented by 1
Data moved from MBR to IR
MBR is now free for further data fetches
Rules for Clock Cycle Grouping
Proper sequence must be followed
Conflicts must be avoided
Indirect Cycle
Steps
MAR <- (IR address)
MBR <- (memory)
IR address <- (MBR address)
Interrupt Cycle
Steps
t1: MBR <- (PC)
t2: MAR <- save-address [somewhere in stack]
t2: PC <- routine-address [interrupt handler]
t3: memory <- (MBR)
Execute Cycle (ADD)
Different for each instruction
Steps
MAR <- (IR address)
MBR <- (memory)
R1 <- R1 + (MBR)
Execute Cycle (ISZ)
Steps
MAR <- (IR address)
MBR <- (memory)
MBR <- (MBR) + 1
memory <- (MBR)
IF (MBR) == 0 then PC <- (PC) + 1
Increment and skip if zero
Execute Cycle (BSA)
Branch and save address
Steps
t1: MAR <- (IR address)
t1: MBR <- (PC)
t2: PC <- (IR address)
t2: memory <- (MBR)
t3: PC <- (PC) + 1
Instruction Cycle
Designates which part of
cycle the processor is in
Codes
00: Fetch
01: Indirect
10: Execute
11: Interrupt
Control of the Processor
Controls the instruction sequence by using unit control
Steps to characterize
Define basic elements of processor
Describe micro-operations processor performs
Determine functions control unit must perform
Basic elements of processor
ALU
Registers
Internal data paths
External data paths
Control Unit
Types of micro-operation
Transfer data between registers
Transfer data from register to external
Transfer data from external to register
Perform arithmetic or logical ops
Functions
Sequencing (flow control)
Execution
Control signals
Clock
Flags
Instruction register
From control bus
Output
Within CPU
Via control bus
Hardwired Implementation
Control unit is a state machine circuit
Input signals transformed to output signals
Control unit inputs
Flags and control bus
Instruction register
Clock
Problems
Complex sequencing & micro-operation logic
Difficult to design and test
Inflexible design
Difficult to add new instructions