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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
Major Advances in Computers
The family concept
Microprogrammed control unit
Cache memory
Pipelining
Multiple processors
Reduced Instruction Set Computer (RISC)
Instruction Execution Characteristics
Characteristics
Operands used
Execution sequencing
Operations performed
Studies by using CISC
Operations
Assignments
Conditional statements
Operands
Mainly local scalar variables
Accessing local variables should be optimized
Procedure calls
Most time consuming
Most variables are local
Implications
Optimizing most used and most time consuming features
Large number of registers
Careful design of pipelines
Reduced instruction set
Compiler-based Register Optimization
Map symbolic registers to real
registers
Symbolic registers that do not overlap can share real registers
Optimization by using graph coloring algorithm
Assign color to each node so that adjacent nodes have different color
Use minimum number of colors
Large Register File
Fastest memory element
Software solution
Require compiler to allocate registers
Allocate based on most used variables in a given time
Requires sophisticated program analysis
Hardware solution
Have more registers
More variables will be in registers
Register Windows
Only uses few parameters
Limited range of depth call
Uses multiple small sets of registers
Implemented by using circular buffer
Global Variables
Have a set of registers for global variables
Allocated by the compiler to memory
Register vs Cache
CISC
Driving force
Moore's Law
Increasingly complex of high level languages
Semantic gap
Intention
Ease compiler writing
Improve execution efficiency
Support more complex HLLs
Disadvantage
Too complex to exploit and optimize
Memory is now cheap
Simple instructions take longer to execute
Complex Instruction Set Computer
RISC
Characteristics
One instruction per cycle
Register to register operations
Few, simple addressing modes
Few, simple instruction formats
Hardwired design (no microcode)
Fixed instruction format
More compile time/effort
Pipelining
Execution
Instruction fetch, execute
Load and store
Instruction fetch, execute, memory
Optimization
Delayed branch
Delayed load
Loop unrolling
