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Control Unit Operation - Coggle Diagram
Control Unit Operation
Micro-operations
A computer executes a program
Fetch/execute cycle
Program Execution
Instruction Cycle
Indirect
Execute
Fetch
Interrupt
Fetch - 4 Registers
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Fetch Sequence
Address of next instruction is in PC
Address (MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on data bus
Data from data bus copied into MBR
PC incremented by 1 (in parallel with data fetch from memory)
Data (instruction) moved from MBR to IR
MBR is now free for further data fetches
Each cycle has a number of steps
Rules for Clock Cycle Grouping
Proper sequence must be followed
Conflicts must be avoided
PC <- (PC) +1 involves addition
Indirect Cycle
Interrupt Cycle
Execute Cycle
Execute Cycle (ADD)
Execute Cycle (ISZ)
Execute Cycle (BSA)
Instruction Cycle
The steps are called micro-operations
Types
Transfer data between registers
Transfer data from register to external
Transfer data from external to register
Perform arithmetic or logical ops
Control of the processor
Basic Elements of Processor
ALU
Registers
Internal data paths
External data paths
Control Unit
Functions
Control unit (CU) is part of the processor
Sequencing (flow control)
Execution
Control Signals
Clock
Instruction register
Flags
From control bus
Output
Within CPU
Cause data movement
Activate specific functions
Via control bus
To memory
To I/O modules
Hardwired implementation
Implementation
Here, CU is a state machine circuit
Input signals transformed to output signals
Control unit inputs
Flags and control bus
Instruction register
Control unit inputs (cont’d)
And assume that the control unit needs to know
which cycle it is at now
We use two bits to ‘symbolize’ which cycle
Problems With Hard Wired Designs
Complex sequencing & micro-operation logic
Difficult to design and test
Inflexible design
Difficult to add new instructions