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Reduced Instruction Set Computers - Coggle Diagram
Reduced Instruction Set Computers
Instruction Execution Characteristics
Operations
Assignments
Conditional statements (IF, LOOP)
Operands
Local scalar variables
Procedure Calls
Local variables
Implications
The Use of a Large Register File
Register Windows
Overlapping register windows
Circular buffer - register windows
Global Variables
Large Register File versus Cache
Large Register File
All local scalars
Individual variables
Compiler-assigned global variables
Save/Restore based on procedure nesting depth
Register addressing
Cache
Recently-used local scalars
Blocks of memory
Recently-used global variables
Save/Restore based on cache replacement algorithm
Memory addressing
Solution
Software solution
Hardware solution
Local Variables Register
Compiler-Based Register Optimization
Graph coloring approach
Nodes
Edges
Reduced Instruction Set Architecture
Why CISC?
Characteristics of Reduced Instruction Set Architectures
One instruction per cycle
Register-to-register operations
Simple addressing modes
Simple instruction formats
Hardwired design (no microcode)
Fixed instruction format
More compile time / effort
CISC versus RISC Characteristics
RISC Characteristics
Instruction decode complexity
Ease or difficulty of pipelining
Ability to take good advantage of compilers
Risc Pipelining
Pipelining with Regular Instructions
Register to register instructions
I = Instruction Fetch
E = Execute
Load and store operations
I: Instruction fetch.
E: Execute. Calculates memory address
D: Memory. Register-to-memory or memory-to-register operation
Optimization of Pipelining
Delayed branch
Delayed load
Loop unrolling
Optimized delayed branch
MIPS R4000
Instruction Set
Instruction Pipeline
Instruction fetch first half
Instruction fetch second half
Register file
Instruction execute
Data cache first
Data cache second
Tag check
Write back
SPARC
SPARC Register Set
Instruction Set
Load/Store Instructions
Shift Instructions
Boolean Instructions
Arithmetic Instructions
Jump/Branch Instructions
Miscellaneous Instructions
Instruction Format
RISC versus CISC Controversy
Quantitative
Attempts to compare program size and execution speed of programs
Qualitative
Examins issues such as high-level language support and optimum
use of VLSI real estate
Problems
No pair of RISC and CISC that are directly comparable
No definitive set of test programs
Difficult to separate hardware effects from complier
effects
Most comparisons done on “toy” rather than production
machines
Most commercial devices are a mixture